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Searched refs:ctz_imm (Results 1 – 3 of 3) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_riscv64.cc1469 int ctz_imm = CTZ(abs_imm); in DivRemByPowerOfTwo() local
1470 DCHECK_GE(ctz_imm, 1); // Division by +/-1 is handled by `DivRemOneOrMinusOne()`. in DivRemByPowerOfTwo()
1476 if (type == DataType::Type::kInt32 || ctz_imm == 1) { in DivRemByPowerOfTwo()
1479 DCHECK_IMPLIES(type == DataType::Type::kInt32, ctz_imm < 32); in DivRemByPowerOfTwo()
1480 __ Srli(tmp, dividend, 64 - ctz_imm); in DivRemByPowerOfTwo()
1484 __ Srli(tmp, tmp, 64 - ctz_imm); in DivRemByPowerOfTwo()
1489 __ Srai(out, tmp, ctz_imm); in DivRemByPowerOfTwo()
1494 if (ctz_imm <= 11) { in DivRemByPowerOfTwo()
Dcode_generator_arm_vixl.cc4515 int ctz_imm = CTZ(abs_imm); in DivRemByPowerOfTwo() local
4517 auto generate_div_code = [this, imm, ctz_imm](vixl32::Register out, vixl32::Register in) { in DivRemByPowerOfTwo()
4518 __ Asr(out, in, ctz_imm); in DivRemByPowerOfTwo()
4562 __ Ubfx(out, dividend, 0, ctz_imm); in DivRemByPowerOfTwo()
4568 if (ctz_imm > 1) { in DivRemByPowerOfTwo()
4572 __ Add(out, dividend, Operand(add_right_input, vixl32::LSR, 32 - ctz_imm)); in DivRemByPowerOfTwo()
4577 __ Bfc(out, 0, ctz_imm); in DivRemByPowerOfTwo()
Dcode_generator_arm64.cc3394 int ctz_imm = CTZ(abs_imm); in FOR_EACH_CONDITION_INSTRUCTION() local
3396 __ Asr(out, final_dividend, ctz_imm); in FOR_EACH_CONDITION_INSTRUCTION()
3398 __ Neg(out, Operand(final_dividend, ASR, ctz_imm)); in FOR_EACH_CONDITION_INSTRUCTION()