| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64.h | 263 void Jalr(XRegister rd, XRegister rs1, int32_t offset);
266 void Beq(XRegister rs1, XRegister rs2, int32_t offset);
267 void Bne(XRegister rs1, XRegister rs2, int32_t offset);
268 void Blt(XRegister rs1, XRegister rs2, int32_t offset);
269 void Bge(XRegister rs1, XRegister rs2, int32_t offset);
270 void Bltu(XRegister rs1, XRegister rs2, int32_t offset);
271 void Bgeu(XRegister rs1, XRegister rs2, int32_t offset);
274 void Lb(XRegister rd, XRegister rs1, int32_t offset);
275 void Lh(XRegister rd, XRegister rs1, int32_t offset);
276 void Lw(XRegister rd, XRegister rs1, int32_t offset);
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| D | assembler_riscv64.cc | 100 void Riscv64Assembler::Jalr(XRegister rd, XRegister rs1, int32_t offset) { in Jalr() argument
102 if (rd == RA && rs1 != Zero && offset == 0) { in Jalr()
103 CJalr(rs1); in Jalr()
105 } else if (rd == Zero && rs1 != Zero && offset == 0) { in Jalr()
106 CJr(rs1); in Jalr()
111 EmitI(offset, rs1, 0x0, rd, 0x67); in Jalr()
116 void Riscv64Assembler::Beq(XRegister rs1, XRegister rs2, int32_t offset) { in Beq() argument
118 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Beq()
119 CBeqz(rs1, offset); in Beq()
121 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Beq()
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| D | assembler_riscv64_test.cc | 832 for (XRegister rs1 : GetRegisters()) { in TestAddConst() local
834 srs.ExcludeXRegister(rs1); in TestAddConst()
837 std::string rs1_name = GetRegisterName(rs1); in TestAddConst()
838 std::string tmp_name = GetRegisterName((rs1 != TMP) ? TMP : TMP2); in TestAddConst()
842 emit_op(rd, rs1, imm); in TestAddConst()
848 emit_op(rd, rs1, imm); in TestAddConst()
858 emit_op(rd, rs1, imm); in TestAddConst()
901 for (XRegister rs1 : GetRegisters()) { in RepeatLoadStoreArbitraryOffset() local
902 XRegister tmp = get_temp(rs1); in RepeatLoadStoreArbitraryOffset()
908 srs.ExcludeXRegister(rs1); in RepeatLoadStoreArbitraryOffset()
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| /art/disassembler/ |
| D | disassembler_riscv64.cc | 196 void PrintLoadStoreAddress(uint32_t rs1, int32_t offset);
359 void DisassemblerRiscv64::Printer::PrintLoadStoreAddress(uint32_t rs1, int32_t offset) { in PrintLoadStoreAddress() argument
363 os_ << "(" << XRegName(rs1) << ")"; in PrintLoadStoreAddress()
365 if (rs1 == TR && offset >= 0) { in PrintLoadStoreAddress()
412 uint32_t rs1 = GetRs1(insn32); in Print32Jalr() local
415 if (rd == Zero && rs1 == RA && imm12 == 0) { in Print32Jalr()
418 os_ << "jr " << XRegName(rs1); in Print32Jalr()
420 os_ << "jalr " << XRegName(rs1); in Print32Jalr()
427 os_ << XRegName(rs1); in Print32Jalr()
429 os_ << imm12 << "(" << XRegName(rs1) << ")"; in Print32Jalr()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.h | 288 void FAdd(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
289 void FClass(XRegister rd, FRegister rs1, DataType::Type type);
291 void Load(Location out, XRegister rs1, int32_t offset, DataType::Type type);
292 void Store(Location value, XRegister rs1, int32_t offset, DataType::Type type);
298 XRegister rs1,
303 void ShNAdd(XRegister rd, XRegister rs1, XRegister rs2, DataType::Type type);
394 void FpBinOp(Reg rd, FRegister rs1, FRegister rs2, DataType::Type type);
395 void FSub(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
396 void FDiv(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
397 void FMul(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
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| D | code_generator_riscv64.cc | 797 Reg rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FpBinOp() argument
800 (assembler->*opS)(rd, rs1, rs2); in FpBinOp()
803 (assembler->*opD)(rd, rs1, rs2); in FpBinOp()
808 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FAdd() argument
809 FpBinOp<FRegister, &Riscv64Assembler::FAddS, &Riscv64Assembler::FAddD>(rd, rs1, rs2, type); in FAdd()
813 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FSub() argument
814 FpBinOp<FRegister, &Riscv64Assembler::FSubS, &Riscv64Assembler::FSubD>(rd, rs1, rs2, type); in FSub()
818 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FDiv() argument
819 FpBinOp<FRegister, &Riscv64Assembler::FDivS, &Riscv64Assembler::FDivD>(rd, rs1, rs2, type); in FDiv()
823 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMul() argument
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| D | intrinsics_riscv64.cc | 255 EmitMemoryPeek(invoke, [&](XRegister rd, XRegister rs1) { __ Lb(rd, rs1, 0); }); in VisitMemoryPeekByte() argument
264 EmitMemoryPeek(invoke, [&](XRegister rd, XRegister rs1) { __ Lw(rd, rs1, 0); }); in VisitMemoryPeekIntNative() argument
273 EmitMemoryPeek(invoke, [&](XRegister rd, XRegister rs1) { __ Ld(rd, rs1, 0); }); in VisitMemoryPeekLongNative() argument
282 EmitMemoryPeek(invoke, [&](XRegister rd, XRegister rs1) { __ Lh(rd, rs1, 0); }); in VisitMemoryPeekShortNative() argument
313 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sb(rs2, rs1, 0); }); in VisitMemoryPokeByte() argument
322 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sw(rs2, rs1, 0); }); in VisitMemoryPokeIntNative() argument
331 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sd(rs2, rs1, 0); }); in VisitMemoryPokeLongNative() argument
340 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sh(rs2, rs1, 0); }); in VisitMemoryPokeShortNative() argument
345 XRegister rs1, in GenerateReverseBytes() argument
351 __ Rev8(rd.AsRegister<XRegister>(), rs1); in GenerateReverseBytes()
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