Searched refs:slli (Results 1 – 6 of 6) sorted by relevance
| /art/runtime/interpreter/mterp/riscv64/ |
| D | object.S | 631 slli t0, a0, 63
718 slli $z0, a0, 63
814 slli t0, a0, 63
912 slli $z0, a0, 63
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| D | other.S | 217 slli t1, t1, 48 // t1 := BBBB000000000000
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| D | invoke.S | 756 slli $z2, $z0, 63 // z2 := negative if z0 bit #0 is set (odd)
1395 slli $z1, $z1, 2
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| /art/runtime/arch/riscv64/ |
| D | asm_support_riscv64.S | 827 slli \tmp, \reg, (63 - \bit) // tested bit => sign bit
833 slli \tmp, \reg, (63 - \bit) // tested bit => sign bit
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| D | quick_entrypoints_riscv64.S | 1393 slli \reg, t5, (LOCK_WORD_STATE_FORWARDING_ADDRESS_SHIFT + 32)
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64.cc | 7642 auto slli = [&](XRegister rd, XRegister rs, int32_t imm) { Slli(rd, rs, imm); }; in LoadImmediate() local
7653 auto&& slli, in LoadImmediate()
7661 slli(rd, rd, CTZ(value)); in LoadImmediate()
7683 emit_simple_li_helper(rd, value, addi, addiw, slli, lui); in LoadImmediate()
7699 auto&& slli, in LoadImmediate()
7726 emit_simple_li_helper(rd, value, addi, addiw, slli, lui); in LoadImmediate()
7730 slli(rd, rd, sll_shamts[i]); in LoadImmediate()
7737 emit_with_slli_addi_helper(rd, value, addi, addiw, slli, lui); in LoadImmediate()
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