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Searched refs:vs3 (Results 1 – 2 of 2) sorted by relevance

/art/compiler/utils/riscv64/
Dassembler_riscv64.h700 void VSe8(VRegister vs3, XRegister rs1, VM vm = VM::kUnmasked);
701 void VSe16(VRegister vs3, XRegister rs1, VM vm = VM::kUnmasked);
702 void VSe32(VRegister vs3, XRegister rs1, VM vm = VM::kUnmasked);
703 void VSe64(VRegister vs3, XRegister rs1, VM vm = VM::kUnmasked);
704 void VSm(VRegister vs3, XRegister rs1);
718 void VSse8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm = VM::kUnmasked);
719 void VSse16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm = VM::kUnmasked);
720 void VSse32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm = VM::kUnmasked);
721 void VSse64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm = VM::kUnmasked);
734 void VSoxei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm = VM::kUnmasked);
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Dassembler_riscv64.cc1780 void Riscv64Assembler::VSe8(VRegister vs3, XRegister rs1, VM vm) { in VSe8() argument
1783 EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSe8()
1786 void Riscv64Assembler::VSe16(VRegister vs3, XRegister rs1, VM vm) { in VSe16() argument
1789 EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSe16()
1792 void Riscv64Assembler::VSe32(VRegister vs3, XRegister rs1, VM vm) { in VSe32() argument
1795 EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSe32()
1798 void Riscv64Assembler::VSe64(VRegister vs3, XRegister rs1, VM vm) { in VSe64() argument
1801 EmitR(funct7, 0b00000, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSe64()
1810 void Riscv64Assembler::VSm(VRegister vs3, XRegister rs1) { in VSm() argument
1813 EmitR(funct7, 0b01011, rs1, enum_cast<uint32_t>(VectorWidth::kMask), vs3, 0x27); in VSm()
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