1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef HABANALABS_H_ 8 #define HABANALABS_H_ 9 #include <drm/drm.h> 10 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 11 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 12 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 13 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 14 #define TS_MAX_ELEMENTS_NUM (1 << 20) 15 enum goya_queue_id { 16 GOYA_QUEUE_ID_DMA_0 = 0, 17 GOYA_QUEUE_ID_DMA_1 = 1, 18 GOYA_QUEUE_ID_DMA_2 = 2, 19 GOYA_QUEUE_ID_DMA_3 = 3, 20 GOYA_QUEUE_ID_DMA_4 = 4, 21 GOYA_QUEUE_ID_CPU_PQ = 5, 22 GOYA_QUEUE_ID_MME = 6, 23 GOYA_QUEUE_ID_TPC0 = 7, 24 GOYA_QUEUE_ID_TPC1 = 8, 25 GOYA_QUEUE_ID_TPC2 = 9, 26 GOYA_QUEUE_ID_TPC3 = 10, 27 GOYA_QUEUE_ID_TPC4 = 11, 28 GOYA_QUEUE_ID_TPC5 = 12, 29 GOYA_QUEUE_ID_TPC6 = 13, 30 GOYA_QUEUE_ID_TPC7 = 14, 31 GOYA_QUEUE_ID_SIZE 32 }; 33 enum gaudi_queue_id { 34 GAUDI_QUEUE_ID_DMA_0_0 = 0, 35 GAUDI_QUEUE_ID_DMA_0_1 = 1, 36 GAUDI_QUEUE_ID_DMA_0_2 = 2, 37 GAUDI_QUEUE_ID_DMA_0_3 = 3, 38 GAUDI_QUEUE_ID_DMA_1_0 = 4, 39 GAUDI_QUEUE_ID_DMA_1_1 = 5, 40 GAUDI_QUEUE_ID_DMA_1_2 = 6, 41 GAUDI_QUEUE_ID_DMA_1_3 = 7, 42 GAUDI_QUEUE_ID_CPU_PQ = 8, 43 GAUDI_QUEUE_ID_DMA_2_0 = 9, 44 GAUDI_QUEUE_ID_DMA_2_1 = 10, 45 GAUDI_QUEUE_ID_DMA_2_2 = 11, 46 GAUDI_QUEUE_ID_DMA_2_3 = 12, 47 GAUDI_QUEUE_ID_DMA_3_0 = 13, 48 GAUDI_QUEUE_ID_DMA_3_1 = 14, 49 GAUDI_QUEUE_ID_DMA_3_2 = 15, 50 GAUDI_QUEUE_ID_DMA_3_3 = 16, 51 GAUDI_QUEUE_ID_DMA_4_0 = 17, 52 GAUDI_QUEUE_ID_DMA_4_1 = 18, 53 GAUDI_QUEUE_ID_DMA_4_2 = 19, 54 GAUDI_QUEUE_ID_DMA_4_3 = 20, 55 GAUDI_QUEUE_ID_DMA_5_0 = 21, 56 GAUDI_QUEUE_ID_DMA_5_1 = 22, 57 GAUDI_QUEUE_ID_DMA_5_2 = 23, 58 GAUDI_QUEUE_ID_DMA_5_3 = 24, 59 GAUDI_QUEUE_ID_DMA_6_0 = 25, 60 GAUDI_QUEUE_ID_DMA_6_1 = 26, 61 GAUDI_QUEUE_ID_DMA_6_2 = 27, 62 GAUDI_QUEUE_ID_DMA_6_3 = 28, 63 GAUDI_QUEUE_ID_DMA_7_0 = 29, 64 GAUDI_QUEUE_ID_DMA_7_1 = 30, 65 GAUDI_QUEUE_ID_DMA_7_2 = 31, 66 GAUDI_QUEUE_ID_DMA_7_3 = 32, 67 GAUDI_QUEUE_ID_MME_0_0 = 33, 68 GAUDI_QUEUE_ID_MME_0_1 = 34, 69 GAUDI_QUEUE_ID_MME_0_2 = 35, 70 GAUDI_QUEUE_ID_MME_0_3 = 36, 71 GAUDI_QUEUE_ID_MME_1_0 = 37, 72 GAUDI_QUEUE_ID_MME_1_1 = 38, 73 GAUDI_QUEUE_ID_MME_1_2 = 39, 74 GAUDI_QUEUE_ID_MME_1_3 = 40, 75 GAUDI_QUEUE_ID_TPC_0_0 = 41, 76 GAUDI_QUEUE_ID_TPC_0_1 = 42, 77 GAUDI_QUEUE_ID_TPC_0_2 = 43, 78 GAUDI_QUEUE_ID_TPC_0_3 = 44, 79 GAUDI_QUEUE_ID_TPC_1_0 = 45, 80 GAUDI_QUEUE_ID_TPC_1_1 = 46, 81 GAUDI_QUEUE_ID_TPC_1_2 = 47, 82 GAUDI_QUEUE_ID_TPC_1_3 = 48, 83 GAUDI_QUEUE_ID_TPC_2_0 = 49, 84 GAUDI_QUEUE_ID_TPC_2_1 = 50, 85 GAUDI_QUEUE_ID_TPC_2_2 = 51, 86 GAUDI_QUEUE_ID_TPC_2_3 = 52, 87 GAUDI_QUEUE_ID_TPC_3_0 = 53, 88 GAUDI_QUEUE_ID_TPC_3_1 = 54, 89 GAUDI_QUEUE_ID_TPC_3_2 = 55, 90 GAUDI_QUEUE_ID_TPC_3_3 = 56, 91 GAUDI_QUEUE_ID_TPC_4_0 = 57, 92 GAUDI_QUEUE_ID_TPC_4_1 = 58, 93 GAUDI_QUEUE_ID_TPC_4_2 = 59, 94 GAUDI_QUEUE_ID_TPC_4_3 = 60, 95 GAUDI_QUEUE_ID_TPC_5_0 = 61, 96 GAUDI_QUEUE_ID_TPC_5_1 = 62, 97 GAUDI_QUEUE_ID_TPC_5_2 = 63, 98 GAUDI_QUEUE_ID_TPC_5_3 = 64, 99 GAUDI_QUEUE_ID_TPC_6_0 = 65, 100 GAUDI_QUEUE_ID_TPC_6_1 = 66, 101 GAUDI_QUEUE_ID_TPC_6_2 = 67, 102 GAUDI_QUEUE_ID_TPC_6_3 = 68, 103 GAUDI_QUEUE_ID_TPC_7_0 = 69, 104 GAUDI_QUEUE_ID_TPC_7_1 = 70, 105 GAUDI_QUEUE_ID_TPC_7_2 = 71, 106 GAUDI_QUEUE_ID_TPC_7_3 = 72, 107 GAUDI_QUEUE_ID_NIC_0_0 = 73, 108 GAUDI_QUEUE_ID_NIC_0_1 = 74, 109 GAUDI_QUEUE_ID_NIC_0_2 = 75, 110 GAUDI_QUEUE_ID_NIC_0_3 = 76, 111 GAUDI_QUEUE_ID_NIC_1_0 = 77, 112 GAUDI_QUEUE_ID_NIC_1_1 = 78, 113 GAUDI_QUEUE_ID_NIC_1_2 = 79, 114 GAUDI_QUEUE_ID_NIC_1_3 = 80, 115 GAUDI_QUEUE_ID_NIC_2_0 = 81, 116 GAUDI_QUEUE_ID_NIC_2_1 = 82, 117 GAUDI_QUEUE_ID_NIC_2_2 = 83, 118 GAUDI_QUEUE_ID_NIC_2_3 = 84, 119 GAUDI_QUEUE_ID_NIC_3_0 = 85, 120 GAUDI_QUEUE_ID_NIC_3_1 = 86, 121 GAUDI_QUEUE_ID_NIC_3_2 = 87, 122 GAUDI_QUEUE_ID_NIC_3_3 = 88, 123 GAUDI_QUEUE_ID_NIC_4_0 = 89, 124 GAUDI_QUEUE_ID_NIC_4_1 = 90, 125 GAUDI_QUEUE_ID_NIC_4_2 = 91, 126 GAUDI_QUEUE_ID_NIC_4_3 = 92, 127 GAUDI_QUEUE_ID_NIC_5_0 = 93, 128 GAUDI_QUEUE_ID_NIC_5_1 = 94, 129 GAUDI_QUEUE_ID_NIC_5_2 = 95, 130 GAUDI_QUEUE_ID_NIC_5_3 = 96, 131 GAUDI_QUEUE_ID_NIC_6_0 = 97, 132 GAUDI_QUEUE_ID_NIC_6_1 = 98, 133 GAUDI_QUEUE_ID_NIC_6_2 = 99, 134 GAUDI_QUEUE_ID_NIC_6_3 = 100, 135 GAUDI_QUEUE_ID_NIC_7_0 = 101, 136 GAUDI_QUEUE_ID_NIC_7_1 = 102, 137 GAUDI_QUEUE_ID_NIC_7_2 = 103, 138 GAUDI_QUEUE_ID_NIC_7_3 = 104, 139 GAUDI_QUEUE_ID_NIC_8_0 = 105, 140 GAUDI_QUEUE_ID_NIC_8_1 = 106, 141 GAUDI_QUEUE_ID_NIC_8_2 = 107, 142 GAUDI_QUEUE_ID_NIC_8_3 = 108, 143 GAUDI_QUEUE_ID_NIC_9_0 = 109, 144 GAUDI_QUEUE_ID_NIC_9_1 = 110, 145 GAUDI_QUEUE_ID_NIC_9_2 = 111, 146 GAUDI_QUEUE_ID_NIC_9_3 = 112, 147 GAUDI_QUEUE_ID_SIZE 148 }; 149 enum gaudi2_queue_id { 150 GAUDI2_QUEUE_ID_PDMA_0_0 = 0, 151 GAUDI2_QUEUE_ID_PDMA_0_1 = 1, 152 GAUDI2_QUEUE_ID_PDMA_0_2 = 2, 153 GAUDI2_QUEUE_ID_PDMA_0_3 = 3, 154 GAUDI2_QUEUE_ID_PDMA_1_0 = 4, 155 GAUDI2_QUEUE_ID_PDMA_1_1 = 5, 156 GAUDI2_QUEUE_ID_PDMA_1_2 = 6, 157 GAUDI2_QUEUE_ID_PDMA_1_3 = 7, 158 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8, 159 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9, 160 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10, 161 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11, 162 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12, 163 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13, 164 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14, 165 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15, 166 GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16, 167 GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17, 168 GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18, 169 GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19, 170 GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20, 171 GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21, 172 GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22, 173 GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23, 174 GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24, 175 GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25, 176 GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26, 177 GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27, 178 GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28, 179 GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29, 180 GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30, 181 GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31, 182 GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32, 183 GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33, 184 GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34, 185 GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35, 186 GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36, 187 GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37, 188 GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38, 189 GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39, 190 GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40, 191 GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41, 192 GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42, 193 GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43, 194 GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44, 195 GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45, 196 GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46, 197 GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47, 198 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48, 199 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49, 200 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50, 201 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51, 202 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52, 203 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53, 204 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54, 205 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55, 206 GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56, 207 GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57, 208 GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58, 209 GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59, 210 GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60, 211 GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61, 212 GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62, 213 GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63, 214 GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64, 215 GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65, 216 GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66, 217 GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67, 218 GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68, 219 GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69, 220 GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70, 221 GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71, 222 GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72, 223 GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73, 224 GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74, 225 GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75, 226 GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76, 227 GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77, 228 GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78, 229 GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79, 230 GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80, 231 GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81, 232 GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82, 233 GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83, 234 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84, 235 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85, 236 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86, 237 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87, 238 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88, 239 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89, 240 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90, 241 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91, 242 GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92, 243 GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93, 244 GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94, 245 GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95, 246 GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96, 247 GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97, 248 GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98, 249 GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99, 250 GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100, 251 GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101, 252 GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102, 253 GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103, 254 GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104, 255 GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105, 256 GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106, 257 GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107, 258 GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108, 259 GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109, 260 GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110, 261 GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111, 262 GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112, 263 GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113, 264 GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114, 265 GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115, 266 GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116, 267 GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117, 268 GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118, 269 GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119, 270 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120, 271 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121, 272 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122, 273 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123, 274 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124, 275 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125, 276 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126, 277 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127, 278 GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128, 279 GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129, 280 GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130, 281 GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131, 282 GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132, 283 GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133, 284 GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134, 285 GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135, 286 GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136, 287 GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137, 288 GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138, 289 GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139, 290 GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140, 291 GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141, 292 GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142, 293 GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143, 294 GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144, 295 GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145, 296 GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146, 297 GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147, 298 GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148, 299 GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149, 300 GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150, 301 GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151, 302 GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152, 303 GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153, 304 GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154, 305 GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155, 306 GAUDI2_QUEUE_ID_NIC_0_0 = 156, 307 GAUDI2_QUEUE_ID_NIC_0_1 = 157, 308 GAUDI2_QUEUE_ID_NIC_0_2 = 158, 309 GAUDI2_QUEUE_ID_NIC_0_3 = 159, 310 GAUDI2_QUEUE_ID_NIC_1_0 = 160, 311 GAUDI2_QUEUE_ID_NIC_1_1 = 161, 312 GAUDI2_QUEUE_ID_NIC_1_2 = 162, 313 GAUDI2_QUEUE_ID_NIC_1_3 = 163, 314 GAUDI2_QUEUE_ID_NIC_2_0 = 164, 315 GAUDI2_QUEUE_ID_NIC_2_1 = 165, 316 GAUDI2_QUEUE_ID_NIC_2_2 = 166, 317 GAUDI2_QUEUE_ID_NIC_2_3 = 167, 318 GAUDI2_QUEUE_ID_NIC_3_0 = 168, 319 GAUDI2_QUEUE_ID_NIC_3_1 = 169, 320 GAUDI2_QUEUE_ID_NIC_3_2 = 170, 321 GAUDI2_QUEUE_ID_NIC_3_3 = 171, 322 GAUDI2_QUEUE_ID_NIC_4_0 = 172, 323 GAUDI2_QUEUE_ID_NIC_4_1 = 173, 324 GAUDI2_QUEUE_ID_NIC_4_2 = 174, 325 GAUDI2_QUEUE_ID_NIC_4_3 = 175, 326 GAUDI2_QUEUE_ID_NIC_5_0 = 176, 327 GAUDI2_QUEUE_ID_NIC_5_1 = 177, 328 GAUDI2_QUEUE_ID_NIC_5_2 = 178, 329 GAUDI2_QUEUE_ID_NIC_5_3 = 179, 330 GAUDI2_QUEUE_ID_NIC_6_0 = 180, 331 GAUDI2_QUEUE_ID_NIC_6_1 = 181, 332 GAUDI2_QUEUE_ID_NIC_6_2 = 182, 333 GAUDI2_QUEUE_ID_NIC_6_3 = 183, 334 GAUDI2_QUEUE_ID_NIC_7_0 = 184, 335 GAUDI2_QUEUE_ID_NIC_7_1 = 185, 336 GAUDI2_QUEUE_ID_NIC_7_2 = 186, 337 GAUDI2_QUEUE_ID_NIC_7_3 = 187, 338 GAUDI2_QUEUE_ID_NIC_8_0 = 188, 339 GAUDI2_QUEUE_ID_NIC_8_1 = 189, 340 GAUDI2_QUEUE_ID_NIC_8_2 = 190, 341 GAUDI2_QUEUE_ID_NIC_8_3 = 191, 342 GAUDI2_QUEUE_ID_NIC_9_0 = 192, 343 GAUDI2_QUEUE_ID_NIC_9_1 = 193, 344 GAUDI2_QUEUE_ID_NIC_9_2 = 194, 345 GAUDI2_QUEUE_ID_NIC_9_3 = 195, 346 GAUDI2_QUEUE_ID_NIC_10_0 = 196, 347 GAUDI2_QUEUE_ID_NIC_10_1 = 197, 348 GAUDI2_QUEUE_ID_NIC_10_2 = 198, 349 GAUDI2_QUEUE_ID_NIC_10_3 = 199, 350 GAUDI2_QUEUE_ID_NIC_11_0 = 200, 351 GAUDI2_QUEUE_ID_NIC_11_1 = 201, 352 GAUDI2_QUEUE_ID_NIC_11_2 = 202, 353 GAUDI2_QUEUE_ID_NIC_11_3 = 203, 354 GAUDI2_QUEUE_ID_NIC_12_0 = 204, 355 GAUDI2_QUEUE_ID_NIC_12_1 = 205, 356 GAUDI2_QUEUE_ID_NIC_12_2 = 206, 357 GAUDI2_QUEUE_ID_NIC_12_3 = 207, 358 GAUDI2_QUEUE_ID_NIC_13_0 = 208, 359 GAUDI2_QUEUE_ID_NIC_13_1 = 209, 360 GAUDI2_QUEUE_ID_NIC_13_2 = 210, 361 GAUDI2_QUEUE_ID_NIC_13_3 = 211, 362 GAUDI2_QUEUE_ID_NIC_14_0 = 212, 363 GAUDI2_QUEUE_ID_NIC_14_1 = 213, 364 GAUDI2_QUEUE_ID_NIC_14_2 = 214, 365 GAUDI2_QUEUE_ID_NIC_14_3 = 215, 366 GAUDI2_QUEUE_ID_NIC_15_0 = 216, 367 GAUDI2_QUEUE_ID_NIC_15_1 = 217, 368 GAUDI2_QUEUE_ID_NIC_15_2 = 218, 369 GAUDI2_QUEUE_ID_NIC_15_3 = 219, 370 GAUDI2_QUEUE_ID_NIC_16_0 = 220, 371 GAUDI2_QUEUE_ID_NIC_16_1 = 221, 372 GAUDI2_QUEUE_ID_NIC_16_2 = 222, 373 GAUDI2_QUEUE_ID_NIC_16_3 = 223, 374 GAUDI2_QUEUE_ID_NIC_17_0 = 224, 375 GAUDI2_QUEUE_ID_NIC_17_1 = 225, 376 GAUDI2_QUEUE_ID_NIC_17_2 = 226, 377 GAUDI2_QUEUE_ID_NIC_17_3 = 227, 378 GAUDI2_QUEUE_ID_NIC_18_0 = 228, 379 GAUDI2_QUEUE_ID_NIC_18_1 = 229, 380 GAUDI2_QUEUE_ID_NIC_18_2 = 230, 381 GAUDI2_QUEUE_ID_NIC_18_3 = 231, 382 GAUDI2_QUEUE_ID_NIC_19_0 = 232, 383 GAUDI2_QUEUE_ID_NIC_19_1 = 233, 384 GAUDI2_QUEUE_ID_NIC_19_2 = 234, 385 GAUDI2_QUEUE_ID_NIC_19_3 = 235, 386 GAUDI2_QUEUE_ID_NIC_20_0 = 236, 387 GAUDI2_QUEUE_ID_NIC_20_1 = 237, 388 GAUDI2_QUEUE_ID_NIC_20_2 = 238, 389 GAUDI2_QUEUE_ID_NIC_20_3 = 239, 390 GAUDI2_QUEUE_ID_NIC_21_0 = 240, 391 GAUDI2_QUEUE_ID_NIC_21_1 = 241, 392 GAUDI2_QUEUE_ID_NIC_21_2 = 242, 393 GAUDI2_QUEUE_ID_NIC_21_3 = 243, 394 GAUDI2_QUEUE_ID_NIC_22_0 = 244, 395 GAUDI2_QUEUE_ID_NIC_22_1 = 245, 396 GAUDI2_QUEUE_ID_NIC_22_2 = 246, 397 GAUDI2_QUEUE_ID_NIC_22_3 = 247, 398 GAUDI2_QUEUE_ID_NIC_23_0 = 248, 399 GAUDI2_QUEUE_ID_NIC_23_1 = 249, 400 GAUDI2_QUEUE_ID_NIC_23_2 = 250, 401 GAUDI2_QUEUE_ID_NIC_23_3 = 251, 402 GAUDI2_QUEUE_ID_ROT_0_0 = 252, 403 GAUDI2_QUEUE_ID_ROT_0_1 = 253, 404 GAUDI2_QUEUE_ID_ROT_0_2 = 254, 405 GAUDI2_QUEUE_ID_ROT_0_3 = 255, 406 GAUDI2_QUEUE_ID_ROT_1_0 = 256, 407 GAUDI2_QUEUE_ID_ROT_1_1 = 257, 408 GAUDI2_QUEUE_ID_ROT_1_2 = 258, 409 GAUDI2_QUEUE_ID_ROT_1_3 = 259, 410 GAUDI2_QUEUE_ID_CPU_PQ = 260, 411 GAUDI2_QUEUE_ID_SIZE 412 }; 413 enum goya_engine_id { 414 GOYA_ENGINE_ID_DMA_0 = 0, 415 GOYA_ENGINE_ID_DMA_1, 416 GOYA_ENGINE_ID_DMA_2, 417 GOYA_ENGINE_ID_DMA_3, 418 GOYA_ENGINE_ID_DMA_4, 419 GOYA_ENGINE_ID_MME_0, 420 GOYA_ENGINE_ID_TPC_0, 421 GOYA_ENGINE_ID_TPC_1, 422 GOYA_ENGINE_ID_TPC_2, 423 GOYA_ENGINE_ID_TPC_3, 424 GOYA_ENGINE_ID_TPC_4, 425 GOYA_ENGINE_ID_TPC_5, 426 GOYA_ENGINE_ID_TPC_6, 427 GOYA_ENGINE_ID_TPC_7, 428 GOYA_ENGINE_ID_SIZE 429 }; 430 enum gaudi_engine_id { 431 GAUDI_ENGINE_ID_DMA_0 = 0, 432 GAUDI_ENGINE_ID_DMA_1, 433 GAUDI_ENGINE_ID_DMA_2, 434 GAUDI_ENGINE_ID_DMA_3, 435 GAUDI_ENGINE_ID_DMA_4, 436 GAUDI_ENGINE_ID_DMA_5, 437 GAUDI_ENGINE_ID_DMA_6, 438 GAUDI_ENGINE_ID_DMA_7, 439 GAUDI_ENGINE_ID_MME_0, 440 GAUDI_ENGINE_ID_MME_1, 441 GAUDI_ENGINE_ID_MME_2, 442 GAUDI_ENGINE_ID_MME_3, 443 GAUDI_ENGINE_ID_TPC_0, 444 GAUDI_ENGINE_ID_TPC_1, 445 GAUDI_ENGINE_ID_TPC_2, 446 GAUDI_ENGINE_ID_TPC_3, 447 GAUDI_ENGINE_ID_TPC_4, 448 GAUDI_ENGINE_ID_TPC_5, 449 GAUDI_ENGINE_ID_TPC_6, 450 GAUDI_ENGINE_ID_TPC_7, 451 GAUDI_ENGINE_ID_NIC_0, 452 GAUDI_ENGINE_ID_NIC_1, 453 GAUDI_ENGINE_ID_NIC_2, 454 GAUDI_ENGINE_ID_NIC_3, 455 GAUDI_ENGINE_ID_NIC_4, 456 GAUDI_ENGINE_ID_NIC_5, 457 GAUDI_ENGINE_ID_NIC_6, 458 GAUDI_ENGINE_ID_NIC_7, 459 GAUDI_ENGINE_ID_NIC_8, 460 GAUDI_ENGINE_ID_NIC_9, 461 GAUDI_ENGINE_ID_SIZE 462 }; 463 enum gaudi2_engine_id { 464 GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0, 465 GAUDI2_DCORE0_ENGINE_ID_EDMA_1, 466 GAUDI2_DCORE0_ENGINE_ID_MME, 467 GAUDI2_DCORE0_ENGINE_ID_TPC_0, 468 GAUDI2_DCORE0_ENGINE_ID_TPC_1, 469 GAUDI2_DCORE0_ENGINE_ID_TPC_2, 470 GAUDI2_DCORE0_ENGINE_ID_TPC_3, 471 GAUDI2_DCORE0_ENGINE_ID_TPC_4, 472 GAUDI2_DCORE0_ENGINE_ID_TPC_5, 473 GAUDI2_DCORE0_ENGINE_ID_DEC_0, 474 GAUDI2_DCORE0_ENGINE_ID_DEC_1, 475 GAUDI2_DCORE1_ENGINE_ID_EDMA_0, 476 GAUDI2_DCORE1_ENGINE_ID_EDMA_1, 477 GAUDI2_DCORE1_ENGINE_ID_MME, 478 GAUDI2_DCORE1_ENGINE_ID_TPC_0, 479 GAUDI2_DCORE1_ENGINE_ID_TPC_1, 480 GAUDI2_DCORE1_ENGINE_ID_TPC_2, 481 GAUDI2_DCORE1_ENGINE_ID_TPC_3, 482 GAUDI2_DCORE1_ENGINE_ID_TPC_4, 483 GAUDI2_DCORE1_ENGINE_ID_TPC_5, 484 GAUDI2_DCORE1_ENGINE_ID_DEC_0, 485 GAUDI2_DCORE1_ENGINE_ID_DEC_1, 486 GAUDI2_DCORE2_ENGINE_ID_EDMA_0, 487 GAUDI2_DCORE2_ENGINE_ID_EDMA_1, 488 GAUDI2_DCORE2_ENGINE_ID_MME, 489 GAUDI2_DCORE2_ENGINE_ID_TPC_0, 490 GAUDI2_DCORE2_ENGINE_ID_TPC_1, 491 GAUDI2_DCORE2_ENGINE_ID_TPC_2, 492 GAUDI2_DCORE2_ENGINE_ID_TPC_3, 493 GAUDI2_DCORE2_ENGINE_ID_TPC_4, 494 GAUDI2_DCORE2_ENGINE_ID_TPC_5, 495 GAUDI2_DCORE2_ENGINE_ID_DEC_0, 496 GAUDI2_DCORE2_ENGINE_ID_DEC_1, 497 GAUDI2_DCORE3_ENGINE_ID_EDMA_0, 498 GAUDI2_DCORE3_ENGINE_ID_EDMA_1, 499 GAUDI2_DCORE3_ENGINE_ID_MME, 500 GAUDI2_DCORE3_ENGINE_ID_TPC_0, 501 GAUDI2_DCORE3_ENGINE_ID_TPC_1, 502 GAUDI2_DCORE3_ENGINE_ID_TPC_2, 503 GAUDI2_DCORE3_ENGINE_ID_TPC_3, 504 GAUDI2_DCORE3_ENGINE_ID_TPC_4, 505 GAUDI2_DCORE3_ENGINE_ID_TPC_5, 506 GAUDI2_DCORE3_ENGINE_ID_DEC_0, 507 GAUDI2_DCORE3_ENGINE_ID_DEC_1, 508 GAUDI2_DCORE0_ENGINE_ID_TPC_6, 509 GAUDI2_ENGINE_ID_PDMA_0, 510 GAUDI2_ENGINE_ID_PDMA_1, 511 GAUDI2_ENGINE_ID_ROT_0, 512 GAUDI2_ENGINE_ID_ROT_1, 513 GAUDI2_PCIE_ENGINE_ID_DEC_0, 514 GAUDI2_PCIE_ENGINE_ID_DEC_1, 515 GAUDI2_ENGINE_ID_NIC0_0, 516 GAUDI2_ENGINE_ID_NIC0_1, 517 GAUDI2_ENGINE_ID_NIC1_0, 518 GAUDI2_ENGINE_ID_NIC1_1, 519 GAUDI2_ENGINE_ID_NIC2_0, 520 GAUDI2_ENGINE_ID_NIC2_1, 521 GAUDI2_ENGINE_ID_NIC3_0, 522 GAUDI2_ENGINE_ID_NIC3_1, 523 GAUDI2_ENGINE_ID_NIC4_0, 524 GAUDI2_ENGINE_ID_NIC4_1, 525 GAUDI2_ENGINE_ID_NIC5_0, 526 GAUDI2_ENGINE_ID_NIC5_1, 527 GAUDI2_ENGINE_ID_NIC6_0, 528 GAUDI2_ENGINE_ID_NIC6_1, 529 GAUDI2_ENGINE_ID_NIC7_0, 530 GAUDI2_ENGINE_ID_NIC7_1, 531 GAUDI2_ENGINE_ID_NIC8_0, 532 GAUDI2_ENGINE_ID_NIC8_1, 533 GAUDI2_ENGINE_ID_NIC9_0, 534 GAUDI2_ENGINE_ID_NIC9_1, 535 GAUDI2_ENGINE_ID_NIC10_0, 536 GAUDI2_ENGINE_ID_NIC10_1, 537 GAUDI2_ENGINE_ID_NIC11_0, 538 GAUDI2_ENGINE_ID_NIC11_1, 539 GAUDI2_ENGINE_ID_PCIE, 540 GAUDI2_ENGINE_ID_PSOC, 541 GAUDI2_ENGINE_ID_ARC_FARM, 542 GAUDI2_ENGINE_ID_KDMA, 543 GAUDI2_ENGINE_ID_SIZE 544 }; 545 enum hl_goya_pll_index { 546 HL_GOYA_CPU_PLL = 0, 547 HL_GOYA_IC_PLL, 548 HL_GOYA_MC_PLL, 549 HL_GOYA_MME_PLL, 550 HL_GOYA_PCI_PLL, 551 HL_GOYA_EMMC_PLL, 552 HL_GOYA_TPC_PLL, 553 HL_GOYA_PLL_MAX 554 }; 555 enum hl_gaudi_pll_index { 556 HL_GAUDI_CPU_PLL = 0, 557 HL_GAUDI_PCI_PLL, 558 HL_GAUDI_SRAM_PLL, 559 HL_GAUDI_HBM_PLL, 560 HL_GAUDI_NIC_PLL, 561 HL_GAUDI_DMA_PLL, 562 HL_GAUDI_MESH_PLL, 563 HL_GAUDI_MME_PLL, 564 HL_GAUDI_TPC_PLL, 565 HL_GAUDI_IF_PLL, 566 HL_GAUDI_PLL_MAX 567 }; 568 enum hl_gaudi2_pll_index { 569 HL_GAUDI2_CPU_PLL = 0, 570 HL_GAUDI2_PCI_PLL, 571 HL_GAUDI2_SRAM_PLL, 572 HL_GAUDI2_HBM_PLL, 573 HL_GAUDI2_NIC_PLL, 574 HL_GAUDI2_DMA_PLL, 575 HL_GAUDI2_MESH_PLL, 576 HL_GAUDI2_MME_PLL, 577 HL_GAUDI2_TPC_PLL, 578 HL_GAUDI2_IF_PLL, 579 HL_GAUDI2_VID_PLL, 580 HL_GAUDI2_MSS_PLL, 581 HL_GAUDI2_PLL_MAX 582 }; 583 enum hl_goya_dma_direction { 584 HL_DMA_HOST_TO_DRAM, 585 HL_DMA_HOST_TO_SRAM, 586 HL_DMA_DRAM_TO_SRAM, 587 HL_DMA_SRAM_TO_DRAM, 588 HL_DMA_SRAM_TO_HOST, 589 HL_DMA_DRAM_TO_HOST, 590 HL_DMA_DRAM_TO_DRAM, 591 HL_DMA_SRAM_TO_SRAM, 592 HL_DMA_ENUM_MAX 593 }; 594 enum hl_device_status { 595 HL_DEVICE_STATUS_OPERATIONAL, 596 HL_DEVICE_STATUS_IN_RESET, 597 HL_DEVICE_STATUS_MALFUNCTION, 598 HL_DEVICE_STATUS_NEEDS_RESET, 599 HL_DEVICE_STATUS_IN_DEVICE_CREATION, 600 HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE, 601 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE 602 }; 603 enum hl_server_type { 604 HL_SERVER_TYPE_UNKNOWN = 0, 605 HL_SERVER_GAUDI_HLS1 = 1, 606 HL_SERVER_GAUDI_HLS1H = 2, 607 HL_SERVER_GAUDI_TYPE1 = 3, 608 HL_SERVER_GAUDI_TYPE2 = 4, 609 HL_SERVER_GAUDI2_HLS2 = 5, 610 HL_SERVER_GAUDI2_TYPE1 = 7 611 }; 612 #define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0) 613 #define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1) 614 #define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2) 615 #define HL_NOTIFIER_EVENT_CS_TIMEOUT (1ULL << 3) 616 #define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1ULL << 4) 617 #define HL_NOTIFIER_EVENT_USER_ENGINE_ERR (1ULL << 5) 618 #define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6) 619 #define HL_NOTIFIER_EVENT_RAZWI (1ULL << 7) 620 #define HL_NOTIFIER_EVENT_PAGE_FAULT (1ULL << 8) 621 #define HL_NOTIFIER_EVENT_CRITICL_HW_ERR (1ULL << 9) 622 #define HL_NOTIFIER_EVENT_CRITICL_FW_ERR (1ULL << 10) 623 #define HL_INFO_HW_IP_INFO 0 624 #define HL_INFO_HW_EVENTS 1 625 #define HL_INFO_DRAM_USAGE 2 626 #define HL_INFO_HW_IDLE 3 627 #define HL_INFO_DEVICE_STATUS 4 628 #define HL_INFO_DEVICE_UTILIZATION 6 629 #define HL_INFO_HW_EVENTS_AGGREGATE 7 630 #define HL_INFO_CLK_RATE 8 631 #define HL_INFO_RESET_COUNT 9 632 #define HL_INFO_TIME_SYNC 10 633 #define HL_INFO_CS_COUNTERS 11 634 #define HL_INFO_PCI_COUNTERS 12 635 #define HL_INFO_CLK_THROTTLE_REASON 13 636 #define HL_INFO_SYNC_MANAGER 14 637 #define HL_INFO_TOTAL_ENERGY 15 638 #define HL_INFO_PLL_FREQUENCY 16 639 #define HL_INFO_POWER 17 640 #define HL_INFO_OPEN_STATS 18 641 #define HL_INFO_DRAM_REPLACED_ROWS 21 642 #define HL_INFO_DRAM_PENDING_ROWS 22 643 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 644 #define HL_INFO_CS_TIMEOUT_EVENT 24 645 #define HL_INFO_RAZWI_EVENT 25 646 #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26 647 #define HL_INFO_SECURED_ATTESTATION 27 648 #define HL_INFO_REGISTER_EVENTFD 28 649 #define HL_INFO_UNREGISTER_EVENTFD 29 650 #define HL_INFO_GET_EVENTS 30 651 #define HL_INFO_UNDEFINED_OPCODE_EVENT 31 652 #define HL_INFO_ENGINE_STATUS 32 653 #define HL_INFO_PAGE_FAULT_EVENT 33 654 #define HL_INFO_USER_MAPPINGS 34 655 #define HL_INFO_FW_GENERIC_REQ 35 656 #define HL_INFO_HW_ERR_EVENT 36 657 #define HL_INFO_FW_ERR_EVENT 37 658 #define HL_INFO_USER_ENGINE_ERR_EVENT 38 659 #define HL_INFO_DEV_SIGNED 40 660 #define HL_INFO_VERSION_MAX_LEN 128 661 #define HL_INFO_CARD_NAME_MAX_LEN 16 662 #define HL_ENGINES_DATA_MAX_SIZE SZ_1M 663 struct hl_info_hw_ip_info { 664 __u64 sram_base_address; 665 __u64 dram_base_address; 666 __u64 dram_size; 667 __u32 sram_size; 668 __u32 num_of_events; 669 __u32 device_id; 670 __u32 module_id; 671 __u32 decoder_enabled_mask; 672 __u16 first_available_interrupt_id; 673 __u16 server_type; 674 __u32 cpld_version; 675 __u32 psoc_pci_pll_nr; 676 __u32 psoc_pci_pll_nf; 677 __u32 psoc_pci_pll_od; 678 __u32 psoc_pci_pll_div_factor; 679 __u8 tpc_enabled_mask; 680 __u8 dram_enabled; 681 __u8 security_enabled; 682 __u8 mme_master_slave_mode; 683 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 684 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 685 __u64 tpc_enabled_mask_ext; 686 __u64 dram_page_size; 687 __u32 edma_enabled_mask; 688 __u16 number_of_user_interrupts; 689 __u8 reserved1; 690 __u8 reserved2; 691 __u64 reserved3; 692 __u64 device_mem_alloc_default_page_size; 693 __u64 reserved4; 694 __u64 reserved5; 695 __u32 reserved6; 696 __u8 reserved7; 697 __u8 revision_id; 698 __u16 tpc_interrupt_id; 699 __u32 rotator_enabled_mask; 700 __u32 reserved9; 701 __u64 engine_core_interrupt_reg_addr; 702 __u64 reserved_dram_size; 703 }; 704 struct hl_info_dram_usage { 705 __u64 dram_free_mem; 706 __u64 ctx_dram_mem; 707 }; 708 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 4 709 struct hl_info_hw_idle { 710 __u32 is_idle; 711 __u32 busy_engines_mask; 712 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 713 }; 714 struct hl_info_device_status { 715 __u32 status; 716 __u32 pad; 717 }; 718 struct hl_info_device_utilization { 719 __u32 utilization; 720 __u32 pad; 721 }; 722 struct hl_info_clk_rate { 723 __u32 cur_clk_rate_mhz; 724 __u32 max_clk_rate_mhz; 725 }; 726 struct hl_info_reset_count { 727 __u32 hard_reset_cnt; 728 __u32 soft_reset_cnt; 729 }; 730 struct hl_info_time_sync { 731 __u64 device_time; 732 __u64 host_time; 733 __u64 tsc_time; 734 }; 735 struct hl_info_pci_counters { 736 __u64 rx_throughput; 737 __u64 tx_throughput; 738 __u64 replay_cnt; 739 }; 740 enum hl_clk_throttling_type { 741 HL_CLK_THROTTLE_TYPE_POWER, 742 HL_CLK_THROTTLE_TYPE_THERMAL, 743 HL_CLK_THROTTLE_TYPE_MAX 744 }; 745 #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER) 746 #define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL) 747 struct hl_info_clk_throttle { 748 __u32 clk_throttling_reason; 749 __u32 pad; 750 __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX]; 751 __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX]; 752 }; 753 struct hl_info_energy { 754 __u64 total_energy_consumption; 755 }; 756 #define HL_PLL_NUM_OUTPUTS 4 757 struct hl_pll_frequency_info { 758 __u16 output[HL_PLL_NUM_OUTPUTS]; 759 }; 760 struct hl_open_stats_info { 761 __u64 open_counter; 762 __u64 last_open_period_ms; 763 __u8 is_compute_ctx_active; 764 __u8 compute_ctx_in_release; 765 __u8 pad[6]; 766 }; 767 struct hl_power_info { 768 __u64 power; 769 }; 770 struct hl_info_sync_manager { 771 __u32 first_available_sync_object; 772 __u32 first_available_monitor; 773 __u32 first_available_cq; 774 __u32 reserved; 775 }; 776 struct hl_info_cs_counters { 777 __u64 total_out_of_mem_drop_cnt; 778 __u64 ctx_out_of_mem_drop_cnt; 779 __u64 total_parsing_drop_cnt; 780 __u64 ctx_parsing_drop_cnt; 781 __u64 total_queue_full_drop_cnt; 782 __u64 ctx_queue_full_drop_cnt; 783 __u64 total_device_in_reset_drop_cnt; 784 __u64 ctx_device_in_reset_drop_cnt; 785 __u64 total_max_cs_in_flight_drop_cnt; 786 __u64 ctx_max_cs_in_flight_drop_cnt; 787 __u64 total_validation_drop_cnt; 788 __u64 ctx_validation_drop_cnt; 789 }; 790 struct hl_info_last_err_open_dev_time { 791 __s64 timestamp; 792 }; 793 struct hl_info_cs_timeout_event { 794 __s64 timestamp; 795 __u64 seq; 796 }; 797 #define HL_RAZWI_NA_ENG_ID U16_MAX 798 #define HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR 128 799 #define HL_RAZWI_READ BIT(0) 800 #define HL_RAZWI_WRITE BIT(1) 801 #define HL_RAZWI_LBW BIT(2) 802 #define HL_RAZWI_HBW BIT(3) 803 #define HL_RAZWI_RR BIT(4) 804 #define HL_RAZWI_ADDR_DEC BIT(5) 805 struct hl_info_razwi_event { 806 __s64 timestamp; 807 __u64 addr; 808 __u16 engine_id[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR]; 809 __u16 num_of_possible_engines; 810 __u8 flags; 811 __u8 pad[5]; 812 }; 813 #define MAX_QMAN_STREAMS_INFO 4 814 #define OPCODE_INFO_MAX_ADDR_SIZE 8 815 struct hl_info_undefined_opcode_event { 816 __s64 timestamp; 817 __u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE]; 818 __u64 cq_addr; 819 __u32 cq_size; 820 __u32 cb_addr_streams_len; 821 __u32 engine_id; 822 __u32 stream_id; 823 }; 824 struct hl_info_hw_err_event { 825 __s64 timestamp; 826 __u16 event_id; 827 __u16 pad[3]; 828 }; 829 enum hl_info_fw_err_type { 830 HL_INFO_FW_HEARTBEAT_ERR, 831 HL_INFO_FW_REPORTED_ERR, 832 }; 833 struct hl_info_fw_err_event { 834 __s64 timestamp; 835 __u16 err_type; 836 __u16 event_id; 837 __u32 pad; 838 }; 839 struct hl_info_engine_err_event { 840 __s64 timestamp; 841 __u16 engine_id; 842 __u16 error_count; 843 __u32 pad; 844 }; 845 struct hl_info_dev_memalloc_page_sizes { 846 __u64 page_order_bitmask; 847 }; 848 #define SEC_PCR_DATA_BUF_SZ 256 849 #define SEC_PCR_QUOTE_BUF_SZ 510 850 #define SEC_SIGNATURE_BUF_SZ 255 851 #define SEC_PUB_DATA_BUF_SZ 510 852 #define SEC_CERTIFICATE_BUF_SZ 2046 853 #define SEC_DEV_INFO_BUF_SZ 5120 854 struct hl_info_sec_attest { 855 __u32 nonce; 856 __u16 pcr_quote_len; 857 __u16 pub_data_len; 858 __u16 certificate_len; 859 __u8 pcr_num_reg; 860 __u8 pcr_reg_len; 861 __u8 quote_sig_len; 862 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; 863 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; 864 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; 865 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 866 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 867 __u8 pad0[2]; 868 }; 869 struct hl_info_signed { 870 __u32 nonce; 871 __u16 pub_data_len; 872 __u16 certificate_len; 873 __u8 info_sig_len; 874 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 875 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 876 __u8 info_sig[SEC_SIGNATURE_BUF_SZ]; 877 __u16 dev_info_len; 878 __u8 dev_info[SEC_DEV_INFO_BUF_SZ]; 879 __u8 pad[2]; 880 }; 881 struct hl_page_fault_info { 882 __s64 timestamp; 883 __u64 addr; 884 __u16 engine_id; 885 __u8 pad[6]; 886 }; 887 struct hl_user_mapping { 888 __u64 dev_va; 889 __u64 size; 890 }; 891 enum gaudi_dcores { 892 HL_GAUDI_WS_DCORE, 893 HL_GAUDI_WN_DCORE, 894 HL_GAUDI_EN_DCORE, 895 HL_GAUDI_ES_DCORE 896 }; 897 struct hl_info_args { 898 __u64 return_pointer; 899 __u32 return_size; 900 __u32 op; 901 union { 902 __u32 dcore_id; 903 __u32 ctx_id; 904 __u32 period_ms; 905 __u32 pll_index; 906 __u32 eventfd; 907 __u32 user_buffer_actual_size; 908 __u32 sec_attest_nonce; 909 __u32 array_size; 910 __u32 fw_sub_opcode; 911 }; 912 __u32 pad; 913 }; 914 #define HL_CB_OP_CREATE 0 915 #define HL_CB_OP_DESTROY 1 916 #define HL_CB_OP_INFO 2 917 #define HL_MAX_CB_SIZE (0x200000 - 32) 918 #define HL_CB_FLAGS_MAP 0x1 919 #define HL_CB_FLAGS_GET_DEVICE_VA 0x2 920 struct hl_cb_in { 921 __u64 cb_handle; 922 __u32 op; 923 __u32 cb_size; 924 __u32 ctx_id; 925 __u32 flags; 926 }; 927 struct hl_cb_out { 928 union { 929 __u64 cb_handle; 930 union { 931 struct { 932 __u32 usage_cnt; 933 __u32 pad; 934 }; 935 __u64 device_va; 936 }; 937 }; 938 }; 939 union hl_cb_args { 940 struct hl_cb_in in; 941 struct hl_cb_out out; 942 }; 943 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 944 struct hl_cs_chunk { 945 union { 946 __u64 cb_handle; 947 __u64 signal_seq_arr; 948 __u64 encaps_signal_seq; 949 }; 950 __u32 queue_index; 951 union { 952 __u32 cb_size; 953 __u32 num_signal_seq_arr; 954 __u32 encaps_signal_offset; 955 }; 956 __u32 cs_chunk_flags; 957 __u32 collective_engine_id; 958 __u32 pad[10]; 959 }; 960 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 961 #define HL_CS_FLAGS_SIGNAL 0x2 962 #define HL_CS_FLAGS_WAIT 0x4 963 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 964 #define HL_CS_FLAGS_TIMESTAMP 0x20 965 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 966 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 967 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 968 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 969 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 970 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 971 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 972 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 973 #define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000 974 #define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000 975 #define HL_CS_FLAGS_ENGINES_COMMAND 0x10000 976 #define HL_CS_STATUS_SUCCESS 0 977 #define HL_MAX_JOBS_PER_CS 512 978 enum hl_engine_command { 979 HL_ENGINE_CORE_HALT = 1, 980 HL_ENGINE_CORE_RUN = 2, 981 HL_ENGINE_STALL = 3, 982 HL_ENGINE_RESUME = 4, 983 HL_ENGINE_COMMAND_MAX 984 }; 985 struct hl_cs_in { 986 union { 987 struct { 988 __u64 chunks_restore; 989 __u64 chunks_execute; 990 }; 991 struct { 992 __u64 engine_cores; 993 __u32 num_engine_cores; 994 __u32 core_command; 995 }; 996 struct { 997 __u64 engines; 998 __u32 num_engines; 999 __u32 engine_command; 1000 }; 1001 }; 1002 union { 1003 __u64 seq; 1004 __u32 encaps_sig_handle_id; 1005 struct { 1006 __u32 encaps_signals_count; 1007 __u32 encaps_signals_q_idx; 1008 }; 1009 }; 1010 __u32 num_chunks_restore; 1011 __u32 num_chunks_execute; 1012 __u32 timeout; 1013 __u32 cs_flags; 1014 __u32 ctx_id; 1015 __u8 pad[4]; 1016 }; 1017 struct hl_cs_out { 1018 union { 1019 __u64 seq; 1020 struct { 1021 __u32 handle_id; 1022 __u32 count; 1023 }; 1024 }; 1025 __u32 status; 1026 __u32 sob_base_addr_offset; 1027 __u16 sob_count_before_submission; 1028 __u16 pad[3]; 1029 }; 1030 union hl_cs_args { 1031 struct hl_cs_in in; 1032 struct hl_cs_out out; 1033 }; 1034 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 1035 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 1036 #define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0xFFF00000 1037 #define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0xFFE00000 1038 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 1039 #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10 1040 #define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20 1041 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 1042 struct hl_wait_cs_in { 1043 union { 1044 struct { 1045 __u64 seq; 1046 __u64 timeout_us; 1047 }; 1048 struct { 1049 union { 1050 __u64 addr; 1051 __u64 cq_counters_handle; 1052 }; 1053 __u64 target; 1054 }; 1055 }; 1056 __u32 ctx_id; 1057 __u32 flags; 1058 union { 1059 struct { 1060 __u8 seq_arr_len; 1061 __u8 pad[7]; 1062 }; 1063 __u64 interrupt_timeout_us; 1064 }; 1065 __u64 cq_counters_offset; 1066 __u64 timestamp_handle; 1067 __u64 timestamp_offset; 1068 }; 1069 #define HL_WAIT_CS_STATUS_COMPLETED 0 1070 #define HL_WAIT_CS_STATUS_BUSY 1 1071 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 1072 #define HL_WAIT_CS_STATUS_ABORTED 3 1073 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 1074 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 1075 struct hl_wait_cs_out { 1076 __u32 status; 1077 __u32 flags; 1078 __s64 timestamp_nsec; 1079 __u32 cs_completion_map; 1080 __u32 pad; 1081 }; 1082 union hl_wait_cs_args { 1083 struct hl_wait_cs_in in; 1084 struct hl_wait_cs_out out; 1085 }; 1086 #define HL_MEM_OP_ALLOC 0 1087 #define HL_MEM_OP_FREE 1 1088 #define HL_MEM_OP_MAP 2 1089 #define HL_MEM_OP_UNMAP 3 1090 #define HL_MEM_OP_MAP_BLOCK 4 1091 #define HL_MEM_OP_EXPORT_DMABUF_FD 5 1092 #define HL_MEM_OP_TS_ALLOC 6 1093 #define HL_MEM_CONTIGUOUS 0x1 1094 #define HL_MEM_SHARED 0x2 1095 #define HL_MEM_USERPTR 0x4 1096 #define HL_MEM_FORCE_HINT 0x8 1097 #define HL_MEM_PREFETCH 0x40 1098 struct hl_mem_in { 1099 union { 1100 struct { 1101 __u64 mem_size; 1102 __u64 page_size; 1103 } alloc; 1104 struct { 1105 __u64 handle; 1106 } free; 1107 struct { 1108 __u64 hint_addr; 1109 __u64 handle; 1110 } map_device; 1111 struct { 1112 __u64 host_virt_addr; 1113 __u64 hint_addr; 1114 __u64 mem_size; 1115 } map_host; 1116 struct { 1117 __u64 block_addr; 1118 } map_block; 1119 struct { 1120 __u64 device_virt_addr; 1121 } unmap; 1122 struct { 1123 __u64 addr; 1124 __u64 mem_size; 1125 __u64 offset; 1126 } export_dmabuf_fd; 1127 }; 1128 __u32 op; 1129 __u32 flags; 1130 __u32 ctx_id; 1131 __u32 num_of_elements; 1132 }; 1133 struct hl_mem_out { 1134 union { 1135 __u64 device_virt_addr; 1136 __u64 handle; 1137 struct { 1138 __u64 block_handle; 1139 __u32 block_size; 1140 __u32 pad; 1141 }; 1142 __s32 fd; 1143 }; 1144 }; 1145 union hl_mem_args { 1146 struct hl_mem_in in; 1147 struct hl_mem_out out; 1148 }; 1149 #define HL_DEBUG_MAX_AUX_VALUES 10 1150 struct hl_debug_params_etr { 1151 __u64 buffer_address; 1152 __u64 buffer_size; 1153 __u32 sink_mode; 1154 __u32 pad; 1155 }; 1156 struct hl_debug_params_etf { 1157 __u64 buffer_address; 1158 __u64 buffer_size; 1159 __u32 sink_mode; 1160 __u32 pad; 1161 }; 1162 struct hl_debug_params_stm { 1163 __u64 he_mask; 1164 __u64 sp_mask; 1165 __u32 id; 1166 __u32 frequency; 1167 }; 1168 struct hl_debug_params_bmon { 1169 __u64 start_addr0; 1170 __u64 addr_mask0; 1171 __u64 start_addr1; 1172 __u64 addr_mask1; 1173 __u32 bw_win; 1174 __u32 win_capture; 1175 __u32 id; 1176 __u32 control; 1177 __u64 start_addr2; 1178 __u64 end_addr2; 1179 __u64 start_addr3; 1180 __u64 end_addr3; 1181 }; 1182 struct hl_debug_params_spmu { 1183 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 1184 __u32 event_types_num; 1185 __u32 pmtrc_val; 1186 __u32 trc_ctrl_host_val; 1187 __u32 trc_en_host_val; 1188 }; 1189 #define HL_DEBUG_OP_ETR 0 1190 #define HL_DEBUG_OP_ETF 1 1191 #define HL_DEBUG_OP_STM 2 1192 #define HL_DEBUG_OP_FUNNEL 3 1193 #define HL_DEBUG_OP_BMON 4 1194 #define HL_DEBUG_OP_SPMU 5 1195 #define HL_DEBUG_OP_TIMESTAMP 6 1196 #define HL_DEBUG_OP_SET_MODE 7 1197 struct hl_debug_args { 1198 __u64 input_ptr; 1199 __u64 output_ptr; 1200 __u32 input_size; 1201 __u32 output_size; 1202 __u32 op; 1203 __u32 reg_idx; 1204 __u32 enable; 1205 __u32 ctx_id; 1206 }; 1207 #define HL_IOCTL_INFO 0x00 1208 #define HL_IOCTL_CB 0x01 1209 #define HL_IOCTL_CS 0x02 1210 #define HL_IOCTL_WAIT_CS 0x03 1211 #define HL_IOCTL_MEMORY 0x04 1212 #define HL_IOCTL_DEBUG 0x05 1213 #define DRM_IOCTL_HL_INFO DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_INFO, struct hl_info_args) 1214 #define DRM_IOCTL_HL_CB DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CB, union hl_cb_args) 1215 #define DRM_IOCTL_HL_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CS, union hl_cs_args) 1216 #define DRM_IOCTL_HL_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_WAIT_CS, union hl_wait_cs_args) 1217 #define DRM_IOCTL_HL_MEMORY DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_MEMORY, union hl_mem_args) 1218 #define DRM_IOCTL_HL_DEBUG DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_DEBUG, struct hl_debug_args) 1219 #define HL_COMMAND_START (DRM_COMMAND_BASE + HL_IOCTL_INFO) 1220 #define HL_COMMAND_END (DRM_COMMAND_BASE + HL_IOCTL_DEBUG + 1) 1221 #endif 1222