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1 /*
2  * This file is auto-generated. Modifications will be lost.
3  *
4  * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5  * for more information.
6  */
7 #ifndef __LINUX_DCBNL_H__
8 #define __LINUX_DCBNL_H__
9 #include <linux/types.h>
10 #define IEEE_8021QAZ_MAX_TCS 8
11 #define IEEE_8021QAZ_TSA_STRICT 0
12 #define IEEE_8021QAZ_TSA_CB_SHAPER 1
13 #define IEEE_8021QAZ_TSA_ETS 2
14 #define IEEE_8021QAZ_TSA_VENDOR 255
15 struct ieee_ets {
16   __u8 willing;
17   __u8 ets_cap;
18   __u8 cbs;
19   __u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
20   __u8 tc_rx_bw[IEEE_8021QAZ_MAX_TCS];
21   __u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
22   __u8 prio_tc[IEEE_8021QAZ_MAX_TCS];
23   __u8 tc_reco_bw[IEEE_8021QAZ_MAX_TCS];
24   __u8 tc_reco_tsa[IEEE_8021QAZ_MAX_TCS];
25   __u8 reco_prio_tc[IEEE_8021QAZ_MAX_TCS];
26 };
27 struct ieee_maxrate {
28   __u64 tc_maxrate[IEEE_8021QAZ_MAX_TCS];
29 };
30 enum dcbnl_cndd_states {
31   DCB_CNDD_RESET = 0,
32   DCB_CNDD_EDGE,
33   DCB_CNDD_INTERIOR,
34   DCB_CNDD_INTERIOR_READY,
35 };
36 struct ieee_qcn {
37   __u8 rpg_enable[IEEE_8021QAZ_MAX_TCS];
38   __u32 rppp_max_rps[IEEE_8021QAZ_MAX_TCS];
39   __u32 rpg_time_reset[IEEE_8021QAZ_MAX_TCS];
40   __u32 rpg_byte_reset[IEEE_8021QAZ_MAX_TCS];
41   __u32 rpg_threshold[IEEE_8021QAZ_MAX_TCS];
42   __u32 rpg_max_rate[IEEE_8021QAZ_MAX_TCS];
43   __u32 rpg_ai_rate[IEEE_8021QAZ_MAX_TCS];
44   __u32 rpg_hai_rate[IEEE_8021QAZ_MAX_TCS];
45   __u32 rpg_gd[IEEE_8021QAZ_MAX_TCS];
46   __u32 rpg_min_dec_fac[IEEE_8021QAZ_MAX_TCS];
47   __u32 rpg_min_rate[IEEE_8021QAZ_MAX_TCS];
48   __u32 cndd_state_machine[IEEE_8021QAZ_MAX_TCS];
49 };
50 struct ieee_qcn_stats {
51   __u64 rppp_rp_centiseconds[IEEE_8021QAZ_MAX_TCS];
52   __u32 rppp_created_rps[IEEE_8021QAZ_MAX_TCS];
53 };
54 struct ieee_pfc {
55   __u8 pfc_cap;
56   __u8 pfc_en;
57   __u8 mbc;
58   __u16 delay;
59   __u64 requests[IEEE_8021QAZ_MAX_TCS];
60   __u64 indications[IEEE_8021QAZ_MAX_TCS];
61 };
62 #define IEEE_8021Q_MAX_PRIORITIES 8
63 #define DCBX_MAX_BUFFERS 8
64 struct dcbnl_buffer {
65   __u8 prio2buffer[IEEE_8021Q_MAX_PRIORITIES];
66   __u32 buffer_size[DCBX_MAX_BUFFERS];
67   __u32 total_size;
68 };
69 #define CEE_DCBX_MAX_PGS 8
70 #define CEE_DCBX_MAX_PRIO 8
71 struct cee_pg {
72   __u8 willing;
73   __u8 error;
74   __u8 pg_en;
75   __u8 tcs_supported;
76   __u8 pg_bw[CEE_DCBX_MAX_PGS];
77   __u8 prio_pg[CEE_DCBX_MAX_PGS];
78 };
79 struct cee_pfc {
80   __u8 willing;
81   __u8 error;
82   __u8 pfc_en;
83   __u8 tcs_supported;
84 };
85 #define IEEE_8021QAZ_APP_SEL_ETHERTYPE 1
86 #define IEEE_8021QAZ_APP_SEL_STREAM 2
87 #define IEEE_8021QAZ_APP_SEL_DGRAM 3
88 #define IEEE_8021QAZ_APP_SEL_ANY 4
89 #define IEEE_8021QAZ_APP_SEL_DSCP 5
90 #define DCB_APP_SEL_PCP 255
91 struct dcb_app {
92   __u8 selector;
93   __u8 priority;
94   __u16 protocol;
95 };
96 #define IEEE_8021QAZ_APP_SEL_MAX 255
97 struct dcb_peer_app_info {
98   __u8 willing;
99   __u8 error;
100 };
101 struct dcbmsg {
102   __u8 dcb_family;
103   __u8 cmd;
104   __u16 dcb_pad;
105 };
106 enum dcbnl_commands {
107   DCB_CMD_UNDEFINED,
108   DCB_CMD_GSTATE,
109   DCB_CMD_SSTATE,
110   DCB_CMD_PGTX_GCFG,
111   DCB_CMD_PGTX_SCFG,
112   DCB_CMD_PGRX_GCFG,
113   DCB_CMD_PGRX_SCFG,
114   DCB_CMD_PFC_GCFG,
115   DCB_CMD_PFC_SCFG,
116   DCB_CMD_SET_ALL,
117   DCB_CMD_GPERM_HWADDR,
118   DCB_CMD_GCAP,
119   DCB_CMD_GNUMTCS,
120   DCB_CMD_SNUMTCS,
121   DCB_CMD_PFC_GSTATE,
122   DCB_CMD_PFC_SSTATE,
123   DCB_CMD_BCN_GCFG,
124   DCB_CMD_BCN_SCFG,
125   DCB_CMD_GAPP,
126   DCB_CMD_SAPP,
127   DCB_CMD_IEEE_SET,
128   DCB_CMD_IEEE_GET,
129   DCB_CMD_GDCBX,
130   DCB_CMD_SDCBX,
131   DCB_CMD_GFEATCFG,
132   DCB_CMD_SFEATCFG,
133   DCB_CMD_CEE_GET,
134   DCB_CMD_IEEE_DEL,
135   __DCB_CMD_ENUM_MAX,
136   DCB_CMD_MAX = __DCB_CMD_ENUM_MAX - 1,
137 };
138 enum dcbnl_attrs {
139   DCB_ATTR_UNDEFINED,
140   DCB_ATTR_IFNAME,
141   DCB_ATTR_STATE,
142   DCB_ATTR_PFC_STATE,
143   DCB_ATTR_PFC_CFG,
144   DCB_ATTR_NUM_TC,
145   DCB_ATTR_PG_CFG,
146   DCB_ATTR_SET_ALL,
147   DCB_ATTR_PERM_HWADDR,
148   DCB_ATTR_CAP,
149   DCB_ATTR_NUMTCS,
150   DCB_ATTR_BCN,
151   DCB_ATTR_APP,
152   DCB_ATTR_IEEE,
153   DCB_ATTR_DCBX,
154   DCB_ATTR_FEATCFG,
155   DCB_ATTR_CEE,
156   __DCB_ATTR_ENUM_MAX,
157   DCB_ATTR_MAX = __DCB_ATTR_ENUM_MAX - 1,
158 };
159 enum ieee_attrs {
160   DCB_ATTR_IEEE_UNSPEC,
161   DCB_ATTR_IEEE_ETS,
162   DCB_ATTR_IEEE_PFC,
163   DCB_ATTR_IEEE_APP_TABLE,
164   DCB_ATTR_IEEE_PEER_ETS,
165   DCB_ATTR_IEEE_PEER_PFC,
166   DCB_ATTR_IEEE_PEER_APP,
167   DCB_ATTR_IEEE_MAXRATE,
168   DCB_ATTR_IEEE_QCN,
169   DCB_ATTR_IEEE_QCN_STATS,
170   DCB_ATTR_DCB_BUFFER,
171   DCB_ATTR_DCB_APP_TRUST_TABLE,
172   DCB_ATTR_DCB_REWR_TABLE,
173   __DCB_ATTR_IEEE_MAX
174 };
175 #define DCB_ATTR_IEEE_MAX (__DCB_ATTR_IEEE_MAX - 1)
176 enum ieee_attrs_app {
177   DCB_ATTR_IEEE_APP_UNSPEC,
178   DCB_ATTR_IEEE_APP,
179   DCB_ATTR_DCB_APP,
180   __DCB_ATTR_IEEE_APP_MAX
181 };
182 #define DCB_ATTR_IEEE_APP_MAX (__DCB_ATTR_IEEE_APP_MAX - 1)
183 enum cee_attrs {
184   DCB_ATTR_CEE_UNSPEC,
185   DCB_ATTR_CEE_PEER_PG,
186   DCB_ATTR_CEE_PEER_PFC,
187   DCB_ATTR_CEE_PEER_APP_TABLE,
188   DCB_ATTR_CEE_TX_PG,
189   DCB_ATTR_CEE_RX_PG,
190   DCB_ATTR_CEE_PFC,
191   DCB_ATTR_CEE_APP_TABLE,
192   DCB_ATTR_CEE_FEAT,
193   __DCB_ATTR_CEE_MAX
194 };
195 #define DCB_ATTR_CEE_MAX (__DCB_ATTR_CEE_MAX - 1)
196 enum peer_app_attr {
197   DCB_ATTR_CEE_PEER_APP_UNSPEC,
198   DCB_ATTR_CEE_PEER_APP_INFO,
199   DCB_ATTR_CEE_PEER_APP,
200   __DCB_ATTR_CEE_PEER_APP_MAX
201 };
202 #define DCB_ATTR_CEE_PEER_APP_MAX (__DCB_ATTR_CEE_PEER_APP_MAX - 1)
203 enum cee_attrs_app {
204   DCB_ATTR_CEE_APP_UNSPEC,
205   DCB_ATTR_CEE_APP,
206   __DCB_ATTR_CEE_APP_MAX
207 };
208 #define DCB_ATTR_CEE_APP_MAX (__DCB_ATTR_CEE_APP_MAX - 1)
209 enum dcbnl_pfc_up_attrs {
210   DCB_PFC_UP_ATTR_UNDEFINED,
211   DCB_PFC_UP_ATTR_0,
212   DCB_PFC_UP_ATTR_1,
213   DCB_PFC_UP_ATTR_2,
214   DCB_PFC_UP_ATTR_3,
215   DCB_PFC_UP_ATTR_4,
216   DCB_PFC_UP_ATTR_5,
217   DCB_PFC_UP_ATTR_6,
218   DCB_PFC_UP_ATTR_7,
219   DCB_PFC_UP_ATTR_ALL,
220   __DCB_PFC_UP_ATTR_ENUM_MAX,
221   DCB_PFC_UP_ATTR_MAX = __DCB_PFC_UP_ATTR_ENUM_MAX - 1,
222 };
223 enum dcbnl_pg_attrs {
224   DCB_PG_ATTR_UNDEFINED,
225   DCB_PG_ATTR_TC_0,
226   DCB_PG_ATTR_TC_1,
227   DCB_PG_ATTR_TC_2,
228   DCB_PG_ATTR_TC_3,
229   DCB_PG_ATTR_TC_4,
230   DCB_PG_ATTR_TC_5,
231   DCB_PG_ATTR_TC_6,
232   DCB_PG_ATTR_TC_7,
233   DCB_PG_ATTR_TC_MAX,
234   DCB_PG_ATTR_TC_ALL,
235   DCB_PG_ATTR_BW_ID_0,
236   DCB_PG_ATTR_BW_ID_1,
237   DCB_PG_ATTR_BW_ID_2,
238   DCB_PG_ATTR_BW_ID_3,
239   DCB_PG_ATTR_BW_ID_4,
240   DCB_PG_ATTR_BW_ID_5,
241   DCB_PG_ATTR_BW_ID_6,
242   DCB_PG_ATTR_BW_ID_7,
243   DCB_PG_ATTR_BW_ID_MAX,
244   DCB_PG_ATTR_BW_ID_ALL,
245   __DCB_PG_ATTR_ENUM_MAX,
246   DCB_PG_ATTR_MAX = __DCB_PG_ATTR_ENUM_MAX - 1,
247 };
248 enum dcbnl_tc_attrs {
249   DCB_TC_ATTR_PARAM_UNDEFINED,
250   DCB_TC_ATTR_PARAM_PGID,
251   DCB_TC_ATTR_PARAM_UP_MAPPING,
252   DCB_TC_ATTR_PARAM_STRICT_PRIO,
253   DCB_TC_ATTR_PARAM_BW_PCT,
254   DCB_TC_ATTR_PARAM_ALL,
255   __DCB_TC_ATTR_PARAM_ENUM_MAX,
256   DCB_TC_ATTR_PARAM_MAX = __DCB_TC_ATTR_PARAM_ENUM_MAX - 1,
257 };
258 enum dcbnl_cap_attrs {
259   DCB_CAP_ATTR_UNDEFINED,
260   DCB_CAP_ATTR_ALL,
261   DCB_CAP_ATTR_PG,
262   DCB_CAP_ATTR_PFC,
263   DCB_CAP_ATTR_UP2TC,
264   DCB_CAP_ATTR_PG_TCS,
265   DCB_CAP_ATTR_PFC_TCS,
266   DCB_CAP_ATTR_GSP,
267   DCB_CAP_ATTR_BCN,
268   DCB_CAP_ATTR_DCBX,
269   __DCB_CAP_ATTR_ENUM_MAX,
270   DCB_CAP_ATTR_MAX = __DCB_CAP_ATTR_ENUM_MAX - 1,
271 };
272 #define DCB_CAP_DCBX_HOST 0x01
273 #define DCB_CAP_DCBX_LLD_MANAGED 0x02
274 #define DCB_CAP_DCBX_VER_CEE 0x04
275 #define DCB_CAP_DCBX_VER_IEEE 0x08
276 #define DCB_CAP_DCBX_STATIC 0x10
277 enum dcbnl_numtcs_attrs {
278   DCB_NUMTCS_ATTR_UNDEFINED,
279   DCB_NUMTCS_ATTR_ALL,
280   DCB_NUMTCS_ATTR_PG,
281   DCB_NUMTCS_ATTR_PFC,
282   __DCB_NUMTCS_ATTR_ENUM_MAX,
283   DCB_NUMTCS_ATTR_MAX = __DCB_NUMTCS_ATTR_ENUM_MAX - 1,
284 };
285 enum dcbnl_bcn_attrs {
286   DCB_BCN_ATTR_UNDEFINED = 0,
287   DCB_BCN_ATTR_RP_0,
288   DCB_BCN_ATTR_RP_1,
289   DCB_BCN_ATTR_RP_2,
290   DCB_BCN_ATTR_RP_3,
291   DCB_BCN_ATTR_RP_4,
292   DCB_BCN_ATTR_RP_5,
293   DCB_BCN_ATTR_RP_6,
294   DCB_BCN_ATTR_RP_7,
295   DCB_BCN_ATTR_RP_ALL,
296   DCB_BCN_ATTR_BCNA_0,
297   DCB_BCN_ATTR_BCNA_1,
298   DCB_BCN_ATTR_ALPHA,
299   DCB_BCN_ATTR_BETA,
300   DCB_BCN_ATTR_GD,
301   DCB_BCN_ATTR_GI,
302   DCB_BCN_ATTR_TMAX,
303   DCB_BCN_ATTR_TD,
304   DCB_BCN_ATTR_RMIN,
305   DCB_BCN_ATTR_W,
306   DCB_BCN_ATTR_RD,
307   DCB_BCN_ATTR_RU,
308   DCB_BCN_ATTR_WRTT,
309   DCB_BCN_ATTR_RI,
310   DCB_BCN_ATTR_C,
311   DCB_BCN_ATTR_ALL,
312   __DCB_BCN_ATTR_ENUM_MAX,
313   DCB_BCN_ATTR_MAX = __DCB_BCN_ATTR_ENUM_MAX - 1,
314 };
315 enum dcb_general_attr_values {
316   DCB_ATTR_VALUE_UNDEFINED = 0xff
317 };
318 #define DCB_APP_IDTYPE_ETHTYPE 0x00
319 #define DCB_APP_IDTYPE_PORTNUM 0x01
320 enum dcbnl_app_attrs {
321   DCB_APP_ATTR_UNDEFINED,
322   DCB_APP_ATTR_IDTYPE,
323   DCB_APP_ATTR_ID,
324   DCB_APP_ATTR_PRIORITY,
325   __DCB_APP_ATTR_ENUM_MAX,
326   DCB_APP_ATTR_MAX = __DCB_APP_ATTR_ENUM_MAX - 1,
327 };
328 #define DCB_FEATCFG_ERROR 0x01
329 #define DCB_FEATCFG_ENABLE 0x02
330 #define DCB_FEATCFG_WILLING 0x04
331 #define DCB_FEATCFG_ADVERTISE 0x08
332 enum dcbnl_featcfg_attrs {
333   DCB_FEATCFG_ATTR_UNDEFINED,
334   DCB_FEATCFG_ATTR_ALL,
335   DCB_FEATCFG_ATTR_PG,
336   DCB_FEATCFG_ATTR_PFC,
337   DCB_FEATCFG_ATTR_APP,
338   __DCB_FEATCFG_ATTR_ENUM_MAX,
339   DCB_FEATCFG_ATTR_MAX = __DCB_FEATCFG_ATTR_ENUM_MAX - 1,
340 };
341 #endif
342