Home
last modified time | relevance | path

Searched refs:ICSR (Results 1 – 8 of 8) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/
Dpendsv.c60 SCB->ICSR = 1UL << 28; in pendsvTrigger()
65 SCB->ICSR = 1UL << 27; in pendsvClear()
70 return !!(SCB->ICSR & (1UL << 28)); in pendsvIsPending()
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm0.h337 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm0plus.h348 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_sc000.h343 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_sc300.h351 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm3.h351 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm4.h398 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm7.h413 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member