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Searched refs:NVIC (Results 1 – 9 of 9) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm0.h505 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
546 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_EnableIRQ()
558 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_DisableIRQ()
574 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); in NVIC_GetPendingIRQ()
586 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_SetPendingIRQ()
598 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ in NVIC_ClearPendingIRQ()
617 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
639 …return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BIT… in NVIC_GetPriority()
Dcore_cm0plus.h612 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
657 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_EnableIRQ()
669 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_DisableIRQ()
685 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); in NVIC_GetPendingIRQ()
697 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_SetPendingIRQ()
709 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ in NVIC_ClearPendingIRQ()
728 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
750 …return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BIT… in NVIC_GetPriority()
Dcore_sc000.h632 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
677 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_EnableIRQ()
689 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_DisableIRQ()
705 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); in NVIC_GetPendingIRQ()
717 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_SetPendingIRQ()
729 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ in NVIC_ClearPendingIRQ()
748 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
770 …return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BIT… in NVIC_GetPriority()
Dcore_sc300.h1246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ in NVIC_EnableIRQ()
1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ in NVIC_DisableIRQ()
1353 …return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /… in NVIC_GetPendingIRQ()
1365 …NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ in NVIC_SetPendingIRQ()
1377 …NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt… in NVIC_ClearPendingIRQ()
1392 …return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /*… in NVIC_GetActive()
1410 …NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Pri… in NVIC_SetPriority()
1431 …return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get prio… in NVIC_GetPriority()
Dcore_cm3.h1266 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
1345 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ in NVIC_EnableIRQ()
1357 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ in NVIC_DisableIRQ()
1373 …return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /… in NVIC_GetPendingIRQ()
1385 …NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ in NVIC_SetPendingIRQ()
1397 …NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt… in NVIC_ClearPendingIRQ()
1412 …return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /*… in NVIC_GetActive()
1430 …NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Pri… in NVIC_SetPriority()
1451 …return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get prio… in NVIC_GetPriority()
Dcore_cm4.h1412 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
1497 …NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_… in NVIC_EnableIRQ()
1509 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ in NVIC_DisableIRQ()
1525 …return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /… in NVIC_GetPendingIRQ()
1537 …NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ in NVIC_SetPendingIRQ()
1549 …NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt… in NVIC_ClearPendingIRQ()
1564 …return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /*… in NVIC_GetActive()
1582 …NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Pri… in NVIC_SetPriority()
1603 …return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get prio… in NVIC_GetPriority()
Dcore_cm7.h1599 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
1684 …NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_… in NVIC_EnableIRQ()
1696 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ in NVIC_DisableIRQ()
1712 …return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /… in NVIC_GetPendingIRQ()
1724 …NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ in NVIC_SetPendingIRQ()
1736 …NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt… in NVIC_ClearPendingIRQ()
1751 …return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /*… in NVIC_GetActive()
1769 …NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Pr… in NVIC_SetPriority()
1790 …return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get pri… in NVIC_GetPriority()
/device/google/cuttlefish_vmm/qemu/x86_64-linux-gnu/usr/share/qemu/
Dtrace-events-all2219 nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recompu…
2220 … bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: v…
2221 nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
2222 nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d …
2223 nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insuffi…
2224 nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
2225 nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int en, int prio) "NVIC s…
2226 nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %…
2227 nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
2228 nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets_secure: %d"
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/device/google/cuttlefish_vmm/qemu/aarch64-linux-gnu/usr/share/qemu/
Dtrace-events-all2219 nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recompu…
2220 … bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: v…
2221 nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
2222 nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d …
2223 nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insuffi…
2224 nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
2225 nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int en, int prio) "NVIC s…
2226 nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %…
2227 nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
2228 nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets_secure: %d"
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