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Searched refs:V4L2_CID_EXYNOS_BASE (Results 1 – 20 of 20) sorted by relevance

/device/google/felix-kernels/5.10/24Q3-12318583/kernel-headers/linux/
Dvideodev2_exynos_media.h22 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
23 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
24 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
25 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
26 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
27 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/caimito-kernels/6.1/24Q3-12157876/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/pantah-kernels/5.10/24Q3-12318583/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/raviole-kernels/5.10/24Q3-12115410/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/bluejay-kernels/5.10/24Q3-12115410/kernel-headers/linux/
Dvideodev2_exynos_media.h22 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
23 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
24 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
25 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
26 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
27 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/comet-kernels/6.1/24Q3-12157876/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/tangorpro-kernels/5.10/24Q3-12318583/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/lynx-kernels/5.10/24Q3-12318583/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/akita-kernels/5.15/24Q3-12065098/kernel-headers/linux/
Dvideodev2_exynos_media.h10 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
11 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
12 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
13 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
14 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
15 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/pantah-kernels/5.10/24Q3-12318583/kernel-headers/linux/
Dvideodev2_exynos_media.h22 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
23 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
24 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
25 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
26 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
27 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/caimito-kernels/6.1/24Q3-12157876/kernel-headers/linux/
Dvideodev2_exynos_media.h10 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
11 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
12 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
13 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
14 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
15 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/akita-kernels/5.15/24Q3-12065098/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/bluejay-kernels/5.10/24Q3-12115410/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/lynx-kernels/5.10/24Q3-12318583/kernel-headers/linux/
Dvideodev2_exynos_media.h22 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
23 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
24 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
25 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
26 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
27 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/felix-kernels/5.10/24Q3-12318583/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/shusky-kernels/5.15/24Q3-12065098/original-kernel-headers/linux/
Dvideodev2_exynos_media.h25 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
28 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
31 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
32 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
33 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
36 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/raviole-kernels/5.10/24Q3-12115410/kernel-headers/linux/
Dvideodev2_exynos_media.h22 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
23 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
24 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
25 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
26 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
27 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/shusky-kernels/5.15/24Q3-12065098/kernel-headers/linux/
Dvideodev2_exynos_media.h10 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
11 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
12 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
13 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
14 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
15 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/tangorpro-kernels/5.10/24Q3-12318583/kernel-headers/linux/
Dvideodev2_exynos_media.h22 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
23 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
24 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
25 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
26 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
27 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)
/device/google/comet-kernels/6.1/24Q3-12157876/kernel-headers/linux/
Dvideodev2_exynos_media.h10 #define V4L2_CID_EXYNOS_BASE (V4L2_CTRL_CLASS_USER | 0x2000) macro
11 #define V4L2_CID_CACHEABLE (V4L2_CID_EXYNOS_BASE + 10)
12 #define V4L2_CID_CSC_EQ_MODE (V4L2_CID_EXYNOS_BASE + 100)
13 #define V4L2_CID_CSC_EQ (V4L2_CID_EXYNOS_BASE + 101)
14 #define V4L2_CID_CSC_RANGE (V4L2_CID_EXYNOS_BASE + 102)
15 #define V4L2_CID_CONTENT_PROTECTION (V4L2_CID_EXYNOS_BASE + 201)