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Searched refs:MachineReg (Results 1 – 25 of 47) sorted by relevance

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/frameworks/libs/binary_translation/backend/common/
Dmachine_ir_test.cc25 TEST(MachineReg, DefaultConstructedRegIsInvalid) { in TEST() argument
26 MachineReg reg; in TEST()
30 TEST(MachineReg, Compare) { in TEST() argument
31 MachineReg reg1{10}; in TEST()
32 MachineReg reg2{12}; in TEST()
33 MachineReg reg3{10}; in TEST()
38 TEST(MachineReg, InvalidRegIsNotVRegsNorSpilledRegNorHardReg) { in TEST() argument
39 MachineReg reg; in TEST()
45 TEST(MachineReg, CreateAndCheckVRegByIndex) { in TEST() argument
46 MachineReg reg = MachineReg::CreateVRegFromIndex(43); in TEST()
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Dreg_alloc.cc281 bool TryAssignHardReg(VRegLifetime* lifetime, MachineReg hard_reg);
283 int ConsiderSpillHardReg(MachineReg hard_reg, VRegLifetime* lifetime);
285 void SpillAndAssignHardReg(MachineReg hard_reg, VRegLifetimeList::iterator curr);
296 int VRegLifetimeAllocator::ConsiderSpillHardReg(MachineReg hard_reg, VRegLifetime* lifetime) { in ConsiderSpillHardReg()
300 bool VRegLifetimeAllocator::TryAssignHardReg(VRegLifetime* curr_lifetime, MachineReg hard_reg) { in TryAssignHardReg()
309 void VRegLifetimeAllocator::SpillAndAssignHardReg(MachineReg hard_reg, in SpillAndAssignHardReg()
325 MachineReg pref_reg = lifetime->FindMoveHint()->hard_reg(); in AllocateLifetime()
331 for (MachineReg hard_reg : *reg_class) { in AllocateLifetime()
341 MachineReg best_reg{0}; in AllocateLifetime()
342 for (MachineReg hard_reg : *reg_class) { in AllocateLifetime()
Dlifetime_analysis.cc21 VRegLifetime* VRegLifetimeAnalysis::GetVRegLifetime(MachineReg r, int begin) { in GetVRegLifetime()
57 MachineReg dst = insn->RegAt(0); in TrySetMoveHint()
61 MachineReg src = insn->RegAt(1); in TrySetMoveHint()
79 MachineReg r = insn->RegAt(i); in AddInsn()
100 MachineReg r = insn->RegAt(i); in AddInsn()
/frameworks/libs/binary_translation/backend/include/berberis/backend/x86_64/
Dmachine_ir.h52 constexpr const MachineReg kMachineRegR8{1};
53 constexpr const MachineReg kMachineRegR9{2};
54 constexpr const MachineReg kMachineRegR10{3};
55 constexpr const MachineReg kMachineRegR11{4};
56 constexpr const MachineReg kMachineRegRSI{5};
57 constexpr const MachineReg kMachineRegRDI{6};
58 constexpr const MachineReg kMachineRegRAX{7};
59 constexpr const MachineReg kMachineRegRBX{8};
60 constexpr const MachineReg kMachineRegRCX{9};
61 constexpr const MachineReg kMachineRegRDX{10};
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Dliveness_analyzer.h37 bool IsLiveIn(const MachineBasicBlock* bb, MachineReg reg) const { in IsLiveIn()
44 MachineReg GetFirstLiveIn(const MachineBasicBlock* bb) const { in GetFirstLiveIn()
48 MachineReg GetNextLiveIn(const MachineBasicBlock* bb, MachineReg prev) const { in GetNextLiveIn()
55 MachineReg vreg = MachineReg::CreateVRegFromIndex(vreg_index); in GetNextLiveIn()
Drename_vregs.h33 ArenaVector<MachineReg>(machine_ir->NumVReg(), kInvalidMachineReg, machine_ir->arena()), in VRegMap()
41 MachineReg Get(MachineReg reg, const MachineBasicBlock* bb);
42 [[nodiscard]] int GetMaxSize(MachineReg reg) const { return max_size_.at(reg.GetVRegIndex()); } in GetMaxSize()
46 ArenaVector<ArenaVector<MachineReg>> map_;
Dmachine_ir_test_corpus.h31 MachineReg,
32 MachineReg>
35 std::tuple<const MachineBasicBlock*, const MachineBasicBlock*, const MachineBasicBlock*, MachineReg>
38 std::tuple<const MachineBasicBlock*, const MachineBasicBlock*, const MachineBasicBlock*, MachineReg>
51 MachineReg>
Dmachine_ir_builder.h47 void GenGet(MachineReg dst_reg, int32_t offset) { in GenGet()
51 void GenPut(int32_t offset, MachineReg src_reg) { in GenPut()
56 void GenGetSimd(MachineReg dst_reg, int32_t offset) { in GenGetSimd()
67 void GenSetSimd(int32_t offset, MachineReg src_reg) { in GenSetSimd()
85 /*may_discard*/ CallImm* GenCallImm(uint64_t imm, MachineReg flag_register) { in GenCallImm()
91 MachineReg flag_register, in GenCallImm()
119 MachineReg arg_reg = arg.reg; in GenCallImmArg()
124 MachineReg renamed_arg_reg = ir()->AllocVReg(); in GenCallImmArg()
Drename_copy_uses.h42 MachineReg renamed;
47 MachineReg Get(MachineReg reg);
48 RenameData& RenameDataForReg(MachineReg reg) { return map_.at(reg.GetVRegIndex()); } in RenameDataForReg()
Dinsn_folding.h32 [[nodiscard]] std::pair<const MachineInsn*, int> Get(MachineReg reg) const { in Get()
38 [[nodiscard]] std::pair<const MachineInsn*, int> Get(MachineReg reg, int use_index) const { in Get()
52 void Set(MachineReg reg, const MachineInsn* insn) { in Set()
59 MachineReg flags_reg_;
73 bool IsRegImm(MachineReg reg, uint64_t* imm) const;
/frameworks/libs/binary_translation/backend/include/berberis/backend/common/
Dmachine_ir.h44 class MachineReg {
47 constexpr MachineReg() : reg_{kInvalidMachineVRegNumber} {} in MachineReg() function
48 constexpr explicit MachineReg(int reg) : reg_{reg} {} in MachineReg() function
49 constexpr MachineReg(const MachineReg&) = default;
50 constexpr MachineReg& operator=(const MachineReg&) = default;
52 constexpr MachineReg(MachineReg&&) = default;
53 constexpr MachineReg& operator=(MachineReg&&) = default;
77 constexpr friend bool operator==(MachineReg left, MachineReg right) {
81 constexpr friend bool operator!=(MachineReg left, MachineReg right) { return !(left == right); }
83 [[nodiscard]] static constexpr MachineReg CreateVRegFromIndex(uint32_t index) { in CreateVRegFromIndex()
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/frameworks/libs/binary_translation/backend/x86_64/
Drename_copy_uses_test.cc38 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
39 MachineReg vreg2 = machine_ir.AllocVReg(); in TEST()
40 MachineReg vreg3 = machine_ir.AllocVReg(); in TEST()
72 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
73 MachineReg vreg2 = machine_ir.AllocVReg(); in TEST()
74 MachineReg vreg3 = machine_ir.AllocVReg(); in TEST()
95 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
96 MachineReg vreg2 = machine_ir.AllocVReg(); in TEST()
97 MachineReg vreg3 = machine_ir.AllocVReg(); in TEST()
98 MachineReg vreg4 = machine_ir.AllocVReg(); in TEST()
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Drename_vregs_local_test.cc37 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
38 MachineReg vreg2 = machine_ir.AllocVReg(); in TEST()
70 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
71 MachineReg vreg2 = machine_ir.AllocVReg(); in TEST()
74 builder.Gen<x86_64::MovqRegReg>(vreg2, MachineReg{4}); in TEST()
89 MachineReg vreg2_renamed = insn->RegAt(0); in TEST()
105 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
106 MachineReg vreg2 = machine_ir.AllocVReg(); in TEST()
128 MachineReg vreg1_renamed = insn->RegAt(0); in TEST()
144 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
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Dcode_emit.cc39 void EmitMovGRegGReg(CodeEmitter* as, MachineReg dst, MachineReg src, int /* size */) { in EmitMovGRegGReg()
43 void EmitMovGRegXReg(CodeEmitter* as, MachineReg dst, MachineReg src, int /* size */) { in EmitMovGRegXReg()
47 void EmitMovGRegMem(CodeEmitter* as, MachineReg dst, MachineReg src, int /* size */) { in EmitMovGRegMem()
53 void EmitMovXRegGReg(CodeEmitter* as, MachineReg dst, MachineReg src, int /* size */) { in EmitMovXRegGReg()
57 void EmitMovXRegXReg(CodeEmitter* as, MachineReg dst, MachineReg src, int /* size */) { in EmitMovXRegXReg()
61 void EmitMovXRegMem(CodeEmitter* as, MachineReg dst, MachineReg src, int size) { in EmitMovXRegMem()
73 void EmitMovMemGReg(CodeEmitter* as, MachineReg dst, MachineReg src, int /* size */) { in EmitMovMemGReg()
79 void EmitMovMemXReg(CodeEmitter* as, MachineReg dst, MachineReg src, int size) { in EmitMovMemXReg()
91 void EmitMovMemMem(CodeEmitter* as, MachineReg dst, MachineReg src, int size) { in EmitMovMemMem()
104 void EmitCopy(CodeEmitter* as, MachineReg dst, MachineReg src, int size) { in EmitCopy()
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Dinsn_folding_test.cc43 MachineReg vreg1 = machine_ir.AllocVReg(); in TryRegRegInsnFolding()
44 MachineReg vreg2 = machine_ir.AllocVReg(); in TryRegRegInsnFolding()
45 MachineReg flags = machine_ir.AllocVReg(); in TryRegRegInsnFolding()
91 MachineReg vreg1 = machine_ir.AllocVReg(); in TryMovInsnFolding()
92 MachineReg vreg2 = machine_ir.AllocVReg(); in TryMovInsnFolding()
140 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
141 MachineReg vreg2 = machine_ir.AllocVReg(); in TEST()
142 MachineReg flags = machine_ir.AllocVReg(); in TEST()
191 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
229 MachineReg vreg1 = machine_ir.AllocVReg(); in TEST()
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Drename_vregs_local.cc30 void Set(MachineReg from_reg, MachineReg to_reg) { vreg_set_[from_reg.GetVRegIndex()] = to_reg; } in Set()
31 [[nodiscard]] MachineReg Get(MachineReg reg) const { return vreg_set_[reg.GetVRegIndex()]; } in Get()
33 [[nodiscard]] bool WasRenamed(MachineReg reg) const { in WasRenamed()
38 bool WasSeen(MachineReg reg) { return vreg_set_[reg.GetVRegIndex()] != kInvalidMachineReg; } in WasSeen()
41 ArenaVector<MachineReg> vreg_set_;
56 MachineReg reg = insn->RegAt(operand_index); in TryRenameRegOperand()
68 MachineReg new_reg = machine_ir->AllocVReg(); in TryRenameRegOperand()
112 MachineReg old_reg = in_reg; in RenameSuccessorsLiveIns()
Dcode.cc122 MachineReg CallImm::IntResultAt(int i) const { in IntResultAt()
132 MachineReg CallImm::XmmResultAt(int i) const { in XmmResultAt()
142 CallImmArg::CallImmArg(MachineReg arg, CallImm::RegType reg_type) in CallImmArg()
164 MachineReg eflags) in PseudoCondBranch()
180 PseudoIndirectJump::PseudoIndirectJump(MachineReg src) in PseudoIndirectJump()
191 PseudoCopy::PseudoCopy(MachineReg dst, MachineReg src, int size) in PseudoCopy()
201 PseudoDefXReg::PseudoDefXReg(MachineReg reg) in PseudoDefXReg()
209 PseudoDefReg::PseudoDefReg(MachineReg reg) in PseudoDefReg()
219 PseudoReadFlags::PseudoReadFlags(WithOverflowEnum with_overflow, MachineReg dst, MachineReg flags) in PseudoReadFlags()
230 PseudoWriteFlags::PseudoWriteFlags(MachineReg src, MachineReg flags) in PseudoWriteFlags()
Drename_copy_uses.cc24 MachineReg RenameCopyUsesMap::Get(MachineReg reg) { in Get()
25 MachineReg renamed = RenameDataForReg(reg).renamed; in Get()
42 MachineReg reg = insn->RegAt(i); in RenameUseIfMapped()
47 MachineReg mapped = Get(reg); in RenameUseIfMapped()
54 MachineReg reg = insn->RegAt(i); in ProcessDef()
Dliveness_analyzer_test.cc42 MachineReg vreg, in ExpectSingleLiveIn()
52 MachineReg vreg1, in ExpectTwoLiveIns()
53 MachineReg vreg2) { in ExpectTwoLiveIns()
57 MachineReg live_in1 = liveness->GetFirstLiveIn(bb); in ExpectTwoLiveIns()
59 MachineReg live_in2 = liveness->GetNextLiveIn(bb, live_in1); in ExpectTwoLiveIns()
70 MachineReg vreg = machine_ir.AllocVReg(); in TEST()
86 explicit FakeInsnWithDefEarlyClobber(MachineReg reg) in FakeInsnWithDefEarlyClobber()
95 MachineReg reg_;
106 MachineReg vreg = machine_ir.AllocVReg(); in TEST()
125 MachineReg vreg = machine_ir.AllocVReg(); in TEST()
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Dmachine_ir_test_corpus.cc32 MachineReg,
33 MachineReg>
36 MachineReg vreg1 = machine_ir->AllocVReg(); in BuildDataFlowAcrossBasicBlocks()
37 MachineReg vreg2 = machine_ir->AllocVReg(); in BuildDataFlowAcrossBasicBlocks()
62 std::tuple<const MachineBasicBlock*, const MachineBasicBlock*, const MachineBasicBlock*, MachineReg>
65 MachineReg vreg = machine_ir->AllocVReg(); in BuildDataFlowFromTwoPreds()
93 std::tuple<const MachineBasicBlock*, const MachineBasicBlock*, const MachineBasicBlock*, MachineReg>
96 MachineReg vreg = machine_ir->AllocVReg(); in BuildDataFlowToTwoSuccs()
130 MachineReg vreg = machine_ir->AllocVReg(); in BuildDiamondControlFlow()
169 MachineReg>
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Drename_vregs.cc41 MachineReg VRegMap::Get(MachineReg reg, const MachineBasicBlock* bb) { in Get()
43 MachineReg& mapped_reg = map_.at(bb->id()).at(reg.GetVRegIndex()); in Get()
54 MachineReg vreg) { in GenInterBasicBlockMove()
55 MachineReg pred_vreg = vreg_map->Get(vreg, pred_bb); in GenInterBasicBlockMove()
56 MachineReg succ_vreg = vreg_map->Get(vreg, succ_bb); in GenInterBasicBlockMove()
/frameworks/libs/binary_translation/backend/testing/include/x86_64/
Dloop_guest_context_optimizer_test_checks.h28 inline MachineReg CheckCopyGetInsnAndObtainMappedReg(MachineInsn* get_insn, in CheckCopyGetInsnAndObtainMappedReg()
29 MachineReg expected_dst) { in CheckCopyGetInsnAndObtainMappedReg()
35 inline MachineReg CheckCopyPutInsnAndObtainMappedReg(MachineInsn* put_insn, in CheckCopyPutInsnAndObtainMappedReg()
36 MachineReg expected_src) { in CheckCopyPutInsnAndObtainMappedReg()
44 MachineReg mapped_reg, in CheckMemRegMap()
53 inline void CheckGetInsn(MachineInsn* insn, MachineOpcode opcode, MachineReg reg, size_t disp) { in CheckGetInsn()
61 inline void CheckPutInsn(MachineInsn* insn, MachineOpcode opcode, MachineReg reg, size_t disp) { in CheckPutInsn()
Dmem_operand.h36 static MemOperand MakeBaseDisp(MachineReg base, int32_t disp) { in MakeBaseDisp()
42 static MemOperand MakeIndexDisp(MachineReg index, int32_t disp) { in MakeIndexDisp()
51 static MemOperand MakeBaseIndexDisp(MachineReg base, MachineReg index, int32_t disp) { in MakeBaseIndexDisp()
57 MachineReg base() const { in base()
62 MachineReg index() const { in index()
85 MachineReg base, in MemOperand()
86 MachineReg index, in MemOperand()
92 const MachineReg base_;
93 const MachineReg index_;
/frameworks/libs/binary_translation/heavy_optimizer/riscv64/
Dcall_intrinsic.h38 void SignExtend64(x86_64::MachineIRBuilder* builder, MachineReg dst, MachineReg src) { in SignExtend64()
63 void SignExtend64Result(x86_64::MachineIRBuilder* builder, MachineReg dst, MachineReg src) { in SignExtend64Result()
75 typename std::enable_if_t<!std::is_same_v<AssemblerType, MachineReg> &&
80 MachineReg reg = builder->ir()->AllocVReg(); in GenPrepareCallImmArg()
81 MachineReg temp_reg = builder->ir()->AllocVReg(); in GenPrepareCallImmArg()
92 typename std::enable_if_t<std::is_same_v<AssemblerType, MachineReg> &&
104 typename std::enable_if_t<std::is_same_v<AssemblerType, MachineReg> &&
108 MachineReg new_reg = builder->ir()->AllocVReg(); in GenPrepareCallImmArg()
123 MachineReg result_ptr, in LoadCallIntrinsicResult()
200 MachineReg flag_register, in CallIntrinsicImpl()
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Dsimd_register.h32 explicit constexpr SimdReg(MachineReg reg) : machine_reg_{reg} {} in SimdReg()
34 [[nodiscard]] MachineReg constexpr machine_reg() const { return machine_reg_; } in machine_reg()
37 MachineReg machine_reg_;

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