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Searched refs:RegAt (Results 1 – 25 of 25) sorted by relevance

/frameworks/libs/binary_translation/backend/x86_64/
Drename_vregs_test.cc50 MachineReg new_vreg = (*it)->RegAt(0); in TEST()
53 EXPECT_EQ(new_vreg, (*it)->RegAt(1)); in TEST()
55 EXPECT_EQ(x86_64::kMachineRegRAX, (*it)->RegAt(0)); in TEST()
83 MachineReg vreg_in_bb1 = (*it)->RegAt(0); in TEST()
88 MachineReg vreg_in_bb2 = (*it)->RegAt(1); in TEST()
92 EXPECT_EQ(x86_64::kMachineRegRAX, (*it)->RegAt(0)); in TEST()
110 MachineReg vreg1_in_bb1 = (*it)->RegAt(0); in TEST()
113 MachineReg vreg2_in_bb1 = (*it)->RegAt(0); in TEST()
125 if ((*it)->RegAt(1) == vreg1_in_bb1) { in TEST()
126 vreg1_in_bb2 = (*it)->RegAt(0); in TEST()
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Dinsn_folding.cc34 MachineReg reg = insn->RegAt(op); in MapDefRegs()
80 folded_insn = machine_ir_->NewInsn<AddqRegImm>(insn->RegAt(0), imm32, insn->RegAt(2)); in NewImmInsnFromRegInsn()
83 folded_insn = machine_ir_->NewInsn<SubqRegImm>(insn->RegAt(0), imm32, insn->RegAt(2)); in NewImmInsnFromRegInsn()
86 folded_insn = machine_ir_->NewInsn<CmpqRegImm>(insn->RegAt(0), imm32, insn->RegAt(2)); in NewImmInsnFromRegInsn()
89 folded_insn = machine_ir_->NewInsn<OrqRegImm>(insn->RegAt(0), imm32, insn->RegAt(2)); in NewImmInsnFromRegInsn()
92 folded_insn = machine_ir_->NewInsn<XorqRegImm>(insn->RegAt(0), imm32, insn->RegAt(2)); in NewImmInsnFromRegInsn()
95 folded_insn = machine_ir_->NewInsn<AndqRegImm>(insn->RegAt(0), imm32, insn->RegAt(2)); in NewImmInsnFromRegInsn()
98 folded_insn = machine_ir_->NewInsn<TestqRegImm>(insn->RegAt(0), imm32, insn->RegAt(2)); in NewImmInsnFromRegInsn()
101 folded_insn = machine_ir_->NewInsn<MovlRegImm>(insn->RegAt(0), imm32); in NewImmInsnFromRegInsn()
104 folded_insn = machine_ir_->NewInsn<AddlRegImm>(insn->RegAt(0), imm32, insn->RegAt(2)); in NewImmInsnFromRegInsn()
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Drename_vregs_local_test.cc55 EXPECT_EQ(vreg1, insn->RegAt(0)); in TEST()
59 EXPECT_EQ(vreg2, insn->RegAt(0)); in TEST()
89 MachineReg vreg2_renamed = insn->RegAt(0); in TEST()
94 EXPECT_EQ(vreg2_renamed, insn->RegAt(1)); in TEST()
124 EXPECT_EQ(vreg1, insn->RegAt(0)); in TEST()
128 MachineReg vreg1_renamed = insn->RegAt(0); in TEST()
133 EXPECT_EQ(vreg1_renamed, insn->RegAt(1)); in TEST()
166 MachineReg vreg1_renamed1 = insn->RegAt(1); in TEST()
169 MachineReg vreg1_renamed2 = insn->RegAt(0); in TEST()
174 EXPECT_EQ(vreg1_renamed2, insn->RegAt(1)); in TEST()
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Dlocal_guest_context_optimizer_test.cc55 auto replaced_reg = store_insn->RegAt(1); in TEST()
56 ASSERT_EQ(store_insn->RegAt(0), x86_64::kMachineRegRBP); in TEST()
60 ASSERT_EQ(load_copy_insn->RegAt(0), reg2); in TEST()
61 ASSERT_EQ(load_copy_insn->RegAt(1), replaced_reg); in TEST()
85 ASSERT_EQ(load_insn->RegAt(0), reg1); in TEST()
86 ASSERT_EQ(load_insn->RegAt(1), x86_64::kMachineRegRBP); in TEST()
90 ASSERT_EQ(copy_insn->RegAt(0), reg2); in TEST()
91 ASSERT_EQ(copy_insn->RegAt(1), reg1); in TEST()
115 ASSERT_EQ(store_insn->RegAt(1), reg2); in TEST()
116 ASSERT_EQ(store_insn->RegAt(0), x86_64::kMachineRegRBP); in TEST()
Drename_copy_uses_test.cc54 EXPECT_EQ(copy_insn->RegAt(1), vreg2); in TEST()
61 EXPECT_EQ(add_insn->RegAt(1), vreg2); in TEST()
84 EXPECT_EQ(add_insn->RegAt(1), vreg2); in TEST()
109 EXPECT_EQ(add_insn->RegAt(1), vreg2); in TEST()
135 EXPECT_EQ(add_insn->RegAt(1), vreg1); in TEST()
160 EXPECT_EQ(add_insn->RegAt(1), vreg1); in TEST()
190 EXPECT_EQ(shift_insn->RegAt(1), vreg1); in TEST()
192 EXPECT_EQ(call_arg_insn->RegAt(0), vreg1); in TEST()
213 EXPECT_EQ(add_insn->RegAt(1), kMachineRegRAX); in TEST()
241 EXPECT_EQ(add_insn->RegAt(1), vreg1); in TEST()
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Dliveness_analyzer.cc69 if (insn->RegAt(i).IsVReg() && insn->RegKindAt(i).IsDef()) { in VisitBasicBlock()
70 running_liveness.Reset(insn->RegAt(i)); in VisitBasicBlock()
74 if (insn->RegAt(i).IsVReg() && insn->RegKindAt(i).IsInput()) { in VisitBasicBlock()
75 running_liveness.Set(insn->RegAt(i)); in VisitBasicBlock()
Drename_copy_uses.cc42 MachineReg reg = insn->RegAt(i); in RenameUseIfMapped()
54 MachineReg reg = insn->RegAt(i); in ProcessDef()
64 auto dst = copy->RegAt(0); in ProcessCopy()
65 auto src = copy->RegAt(1); in ProcessCopy()
Dinsn_folding_test.cc77 EXPECT_EQ(vreg2, folded_insn->RegAt(0)); in TryRegRegInsnFolding()
78 EXPECT_EQ(flags, folded_insn->RegAt(1)); in TryRegRegInsnFolding()
120 EXPECT_EQ(vreg2, folded_insn->RegAt(0)); in TryMovInsnFolding()
160 EXPECT_EQ(vreg1, vreg1_def->RegAt(0)); in TEST()
165 EXPECT_EQ(vreg2, vreg2_def->RegAt(0)); in TEST()
213 EXPECT_EQ(kMachineRegRAX, folded_insn->RegAt(0)); in TEST()
251 EXPECT_EQ(kMachineRegRAX, folded_insn->RegAt(0)); in TEST()
288 EXPECT_EQ(vreg1, folded_insn->RegAt(0)); in TEST()
289 EXPECT_EQ(vreg2, folded_insn->RegAt(1)); in TEST()
510 EXPECT_EQ(vreg2, insn->RegAt(0)); in TEST()
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Dlocal_guest_context_optimizer.cc64 auto dst = insn->RegAt(0); in ReplaceGetAndUpdateMap()
81 auto src = insn->RegAt(1); in ReplacePutAndUpdateMap()
Dcode_emit.cc290 as->Movq(as->rax, x86_64::GetGReg(RegAt(0))); in Emit()
294 EmitIndirectDispatch(as, x86_64::GetGReg(RegAt(0))); in Emit()
298 MachineReg dst = RegAt(0); in Emit()
299 MachineReg src = RegAt(1); in Emit()
Dmachine_ir_opt.cc68 if (insn->RegKindAt(i).IsDef() && is_reg_used[insn->RegAt(i)]) { in AreResultsUsed()
78 is_reg_used.Reset(insn->RegAt(i)); in SetInsnResultsUnused()
86 is_reg_used.Set(insn->RegAt(i)); in SetInsnArgumentsUsed()
Dcode.cc129 return RegAt(kIntResultIndex[i]); in IntResultAt()
139 return RegAt(kXmmResultIndex[i]); in XmmResultAt()
Drename_vregs.cc30 auto reg = insn->RegAt(i); in AssignNewVRegs()
Dloop_guest_context_optimizer.cc59 auto dst = insn->RegAt(0); in ReplaceGetAndUpdateMap()
96 auto src = insn->RegAt(1); in ReplacePutAndUpdateMap()
Dmachine_ir_opt_test.cc57 MachineReg reg_after = insn->RegAt(0); in TEST()
87 MachineReg reg_after = insn->RegAt(0); in TEST()
115 MachineReg reg_after = insn->RegAt(0); in TEST()
146 MachineReg reg_after = insn->RegAt(0); in TEST()
201 MachineReg reg_after = insn->RegAt(0); in TEST()
970 EXPECT_EQ(x86_64::kMachineRegRBX, insn0->RegAt(0)); in TEST()
971 EXPECT_EQ(x86_64::kMachineRegRCX, insn0->RegAt(1)); in TEST()
Drename_vregs_local.cc56 MachineReg reg = insn->RegAt(operand_index); in TryRenameRegOperand()
Dloop_guest_context_optimizer_test.cc718 auto mapped_reg = get_insn->RegAt(0); in TEST()
762 auto mapped_reg = get_insn->RegAt(0); in TEST()
806 auto mapped_reg = get_insn->RegAt(0); in TEST()
862 auto mapped_reg = get_insn->RegAt(0); in TEST()
1029 auto mapped_reg_1 = get_insn_1->RegAt(0); in TEST()
1035 auto mapped_reg_2 = get_insn_2->RegAt(0); in TEST()
/frameworks/libs/binary_translation/backend/testing/include/x86_64/
Dloop_guest_context_optimizer_test_checks.h31 EXPECT_EQ(get_insn->RegAt(0), expected_dst); in CheckCopyGetInsnAndObtainMappedReg()
32 return get_insn->RegAt(1); in CheckCopyGetInsnAndObtainMappedReg()
38 EXPECT_EQ(put_insn->RegAt(1), expected_src); in CheckCopyPutInsnAndObtainMappedReg()
39 return put_insn->RegAt(0); in CheckCopyPutInsnAndObtainMappedReg()
57 EXPECT_EQ(get_insn->RegAt(0), reg); in CheckGetInsn()
65 EXPECT_EQ(put_insn->RegAt(1), reg); in CheckPutInsn()
/frameworks/libs/binary_translation/backend/common/
Dlifetime_analysis.cc57 MachineReg dst = insn->RegAt(0); in TrySetMoveHint()
61 MachineReg src = insn->RegAt(1); in TrySetMoveHint()
79 MachineReg r = insn->RegAt(i); in AddInsn()
100 MachineReg r = insn->RegAt(i); in AddInsn()
Dmachine_ir_opt.cc33 machine_insn->RegAt(0) == machine_insn->RegAt(1); in RemoveNopPseudoCopy()
Dmachine_ir_debug.cc53 MachineReg r = insn->RegAt(i); in GetRegOperandDebugString()
/frameworks/libs/binary_translation/backend/include/berberis/backend/x86_64/
Dmachine_insn_intrinsics.h291 return std::tuple_cat(std::tuple{GetXReg(this->RegAt(reg_idx))},
295 return std::tuple_cat(std::tuple{GetGReg(this->RegAt(reg_idx))},
301 return std::tuple_cat(std::tuple{Assembler::Operand{.base = GetGReg(this->RegAt(reg_idx)),
305 return std::tuple_cat(std::tuple{Assembler::Operand{.base = GetGReg(this->RegAt(reg_idx)),
Dmachine_ir.h167 return RegAt(1) == kCPUStatePointer; in IsCPUStateGet()
190 return RegAt(0) == kCPUStatePointer; in IsCPUStatePut()
/frameworks/libs/binary_translation/backend/include/berberis/backend/common/
Dlifetime.h39 MachineReg GetVReg() const { return pos_.insn()->RegAt(index_); } in GetVReg()
48 if (pos_.insn()->is_copy() && !pos_.insn()->RegAt(0).IsSpilledReg()) { in RewriteVReg()
57 if (pos_.insn()->is_copy() && !pos_.insn()->RegAt(1).IsSpilledReg()) { in RewriteVReg()
Dmachine_ir.h148 [[nodiscard]] MachineReg RegAt(int i) const { return regs[i]; } in RegAt() function
215 [[nodiscard]] MachineReg RegAt(int i) const { in RegAt() function