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Searched refs:v10 (Results 1 – 19 of 19) sorted by relevance

/frameworks/rs/toolkit/
DConvolve_advsimd.S140 uxtl v10.8h, v10.8b
153 smlal v5.4s, v10.4h, v0.h[1]
154 smlal v4.4s, v10.4h, v0.h[2]
155 smlal2 v5.4s, v10.8h, v0.h[2]
156 smlal2 v4.4s, v10.8h, v0.h[3]
183 uxtl v10.8h, v10.8b
196 smlal v5.4s, v10.4h, v1.h[3]
197 smlal v4.4s, v10.4h, v1.h[4]
198 smlal2 v5.4s, v10.8h, v1.h[4]
199 smlal2 v4.4s, v10.8h, v1.h[5]
[all …]
DResize_advsimd.S54 ld1 {v10.8b}, [x6], #8
58 uxtl v10.8h, v10.8b
64 umlal v12.4s, v10.4h, v3.h[2]
65 umlal2 v13.4s, v10.8h, v3.h[2]
82 ld1 {v10.s}[0], [x6], #4
86 uxtl v10.8h, v10.8b
90 umlal v12.4s, v10.4h, v3.h[2]
418 sqrdmulh v10.8h, v9.8h, v8.8h // sxf**3
423 smlsl v11.4s, v10.4h, v30.4h
424 smlsl2 v12.4s, v10.8h, v30.8h
[all …]
DBlend_advsimd.S73 mov v2.16b, v10.16b
124 uqadd v2.16b, v2.16b, v10.16b
136 umull2 v14.8h, v7.16b, v10.16b
137 umull v10.8h, v7.8b, v10.8b
145 rshrn v6.8b, v10.8h, #8
154 uaddw v10.8h, v10.8h, v6.8b
163 rshrn v10.8b, v10.8h, #8
164 rshrn2 v10.16b, v14.8h, #8
170 uqadd v2.16b, v2.16b, v10.16b
180 umull2 v14.8h, v3.16b, v10.16b
[all …]
DYuvToRgb_advsimd.S30 .macro yuvkern, regu=v10, regv=v11
175 ld2 {v10.16b,v11.16b}, [x3], #32
177 ld1 {v10.16b}, [x3], #16
182 \kernel regu=v11, regv=v10
206 movi v10.8b, #0
214 ld1 {v10.d}[1], [x3], #8
220 ld1 {v10.d}[1], [x3], #8
222 ld1 {v10.s}[1], [x3], #4
228 ld1 {v10.s}[1], [x3], #4
230 ld1 {v10.h}[1], [x3], #2
[all …]
DBlur_advsimd.S117 ld1 {v10.16b}, [x10], x2
119 uaddl v16.8h, v10.8b, v11.8b
120 uaddl2 v11.8h, v10.16b, v11.16b
139 ld1 {v10.16b}, [x10], x2
143 uaddl v16.8h, v10.8b, v11.8b
145 uaddl2 v11.8h, v10.16b, v11.16b
228 2: uqrshrn v10.4h, v12.4s, #16 - FRACTION_BITS
230 uqrshrn2 v10.8h, v13.4s, #16 - FRACTION_BITS
289 umlal v14.4s, v10.4h, v1.h[0]
290 umlal2 v15.4s, v10.8h, v1.h[0]
[all …]
DLut3d_advsimd.S69 rshrn v10.4h, v8.4s, #8
70 rshrn2 v10.8h, v9.4s, #8
83 ushll v8.4s, v10.4h, #8
85 umlsl v8.4s, v10.4h, \xr0
87 umlal2 v8.4s, v10.8h, \xr0
179 uxtl v10.4s, v14.4h
183 mla v6.4s, v10.4s, v4.s[3]
DColorMatrix_advsimd.S158 sqshrun v10.4h, v6.4s, #8
159 sqshrun2 v10.8h, v7.4s, #8
175 sqshrun v10.4h, v6.4s, #8
176 sqshrun2 v10.8h, v7.4s, #8
272 vmxx_f32 \i, 1, v10.4s, v12.4s, v0.s[2]
273 vmxx_f32 \i, 2, v10.4s, v13.4s, v1.s[2]
274 vmxx_f32 \i, 4, v10.4s, v14.4s, v2.s[2]
275 vmxx_f32 \i, 8, v10.4s, v15.4s, v3.s[2]
276 vadd_f32 \i, 16, v10.4s, v10.4s, v6.4s, v10.16b, v6.16b
286 vmxx_f32 \i^31, 1, v10.4s, v12.4s, v0.s[2]
[all …]
/frameworks/rs/cpu_ref/
DrsCpuIntrinsics_advsimd_Convolve.S140 uxtl v10.8h, v10.8b
153 smlal v5.4s, v10.4h, v0.h[1]
154 smlal v4.4s, v10.4h, v0.h[2]
155 smlal2 v5.4s, v10.8h, v0.h[2]
156 smlal2 v4.4s, v10.8h, v0.h[3]
183 uxtl v10.8h, v10.8b
196 smlal v5.4s, v10.4h, v1.h[3]
197 smlal v4.4s, v10.4h, v1.h[4]
198 smlal2 v5.4s, v10.8h, v1.h[4]
199 smlal2 v4.4s, v10.8h, v1.h[5]
[all …]
DrsCpuIntrinsics_advsimd_Resize.S54 ld1 {v10.8b}, [x6], #8
58 uxtl v10.8h, v10.8b
64 umlal v12.4s, v10.4h, v3.h[2]
65 umlal2 v13.4s, v10.8h, v3.h[2]
82 ld1 {v10.s}[0], [x6], #4
86 uxtl v10.8h, v10.8b
90 umlal v12.4s, v10.4h, v3.h[2]
418 sqrdmulh v10.8h, v9.8h, v8.8h // sxf**3
423 smlsl v11.4s, v10.4h, v30.4h
424 smlsl2 v12.4s, v10.8h, v30.8h
[all …]
DrsCpuIntrinsics_advsimd_Blend.S68 mov v2.16b, v10.16b
119 uqadd v2.16b, v2.16b, v10.16b
131 umull2 v14.8h, v7.16b, v10.16b
132 umull v10.8h, v7.8b, v10.8b
140 rshrn v6.8b, v10.8h, #8
149 uaddw v10.8h, v10.8h, v6.8b
158 rshrn v10.8b, v10.8h, #8
159 rshrn2 v10.16b, v14.8h, #8
165 uqadd v2.16b, v2.16b, v10.16b
175 umull2 v14.8h, v3.16b, v10.16b
[all …]
DrsCpuIntrinsics_advsimd_YuvToRGB.S30 .macro yuvkern, regu=v10, regv=v11
175 ld2 {v10.16b,v11.16b}, [x3], #32
177 ld1 {v10.16b}, [x3], #16
182 \kernel regu=v11, regv=v10
206 movi v10.8b, #0
214 ld1 {v10.d}[1], [x3], #8
220 ld1 {v10.d}[1], [x3], #8
222 ld1 {v10.s}[1], [x3], #4
228 ld1 {v10.s}[1], [x3], #4
230 ld1 {v10.h}[1], [x3], #2
[all …]
DrsCpuIntrinsics_advsimd_Blur.S117 ld1 {v10.16b}, [x10], x2
119 uaddl v16.8h, v10.8b, v11.8b
120 uaddl2 v11.8h, v10.16b, v11.16b
139 ld1 {v10.16b}, [x10], x2
143 uaddl v16.8h, v10.8b, v11.8b
145 uaddl2 v11.8h, v10.16b, v11.16b
228 2: uqrshrn v10.4h, v12.4s, #16 - FRACTION_BITS
230 uqrshrn2 v10.8h, v13.4s, #16 - FRACTION_BITS
289 umlal v14.4s, v10.4h, v1.h[0]
290 umlal2 v15.4s, v10.8h, v1.h[0]
[all …]
DrsCpuIntrinsics_advsimd_3DLUT.S69 rshrn v10.4h, v8.4s, #8
70 rshrn2 v10.8h, v9.4s, #8
83 ushll v8.4s, v10.4h, #8
85 umlsl v8.4s, v10.4h, \xr0
87 umlal2 v8.4s, v10.8h, \xr0
179 uxtl v10.4s, v14.4h
183 mla v6.4s, v10.4s, v4.s[3]
DrsCpuIntrinsics_advsimd_ColorMatrix.S158 sqshrun v10.4h, v6.4s, #8
159 sqshrun2 v10.8h, v7.4s, #8
175 sqshrun v10.4h, v6.4s, #8
176 sqshrun2 v10.8h, v7.4s, #8
272 vmxx_f32 \i, 1, v10.4s, v12.4s, v0.s[2]
273 vmxx_f32 \i, 2, v10.4s, v13.4s, v1.s[2]
274 vmxx_f32 \i, 4, v10.4s, v14.4s, v2.s[2]
275 vmxx_f32 \i, 8, v10.4s, v15.4s, v3.s[2]
276 vadd_f32 \i, 16, v10.4s, v10.4s, v6.4s, v10.16b, v6.16b
286 vmxx_f32 \i^31, 1, v10.4s, v12.4s, v0.s[2]
[all …]
/frameworks/compile/mclinker/unittests/
DGCFactoryListTraitsTest.cpp62 #define CHECK_LIST_VALUE(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10) \ argument
74 CHECK_NODE_VALUE(v10); \
/frameworks/base/test-junit/src/junit/
DREADME.android3 License File: cpl-v10.html
/frameworks/base/test-junit/
DAndroid.bp28 "src/junit/cpl-v10.html",
/frameworks/base/graphics/java/android/graphics/
DMatrix44.java345 float v10 = dot(mBackingArray[4], mBackingArray[5], mBackingArray[6], mBackingArray[7], in rotate() local
374 mBackingArray[4] = v10; in rotate()
/frameworks/base/tools/aapt2/integration-tests/CommandTests/
Dandroid-33.jarAndroidManifest.xml META-INF/ META-INF/MANIFEST.MF NOTICES/ NOTICES/libcore ...