Searched refs:AND_OPCODE (Results 1 – 10 of 10) sorted by relevance
| /hardware/google/apf/ |
| D | apf.h | 143 #define AND_OPCODE 10 // And, e.g. "and R0,5" macro
|
| D | disassembler.c | 64 [AND_OPCODE] = "and",
235 case AND_OPCODE: in apf_disassemble()
|
| D | apf_interpreter.c | 230 case AND_OPCODE: in accept_packet()
|
| /hardware/google/apf/v4/ |
| D | apf.h | 143 #define AND_OPCODE 10 // And, e.g. "and R0,5" macro
|
| D | apf_interpreter.c | 230 case AND_OPCODE: in accept_packet()
|
| /hardware/google/apf/v7/ |
| D | apf.h | 177 #define AND_OPCODE 10 // And, e.g. "and R0,5" macro
|
| D | apf_interpreter.c | 233 #define AND_OPCODE 10 /* And, e.g. "and R0,5" */ macro
863 case AND_OPCODE: ARITH_REG &= (ctx->v6) ? (u32)arith_signed_imm : arith_imm; break; in do_apf_run()
|
| D | apf_interpreter_source.c | 317 case AND_OPCODE: ARITH_REG &= (ctx->v6) ? (u32)arith_signed_imm : arith_imm; break; in do_apf_run()
|
| /hardware/google/apf/devtools/ |
| D | apf_interpreter.c | 233 #define AND_OPCODE 10 /* And, e.g. "and R0,5" */ macro
863 case AND_OPCODE: ARITH_REG &= (ctx->v6) ? (u32)arith_signed_imm : arith_imm; break; in do_apf_run()
|
| /hardware/google/apf/v6/ |
| D | apf_interpreter.c | 233 #define AND_OPCODE 10 /* And, e.g. "and R0,5" */ macro
853 case AND_OPCODE: ARITH_REG &= (ctx->v6) ? (u32)arith_signed_imm : arith_imm; break; in do_apf_run()
|