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Searched refs:nxpucihal_ctrl (Results 1 – 10 of 10) sorted by relevance

/hardware/nxp/uwb/halimpl/hal/
DphNxpUciHal.cc47 phNxpUciHal_Control_t nxpucihal_ctrl; variable
118 nxpucihal_ctrl.isSkipPacket = 1; in phNxpUciHal_rx_handler_check()
169 if (nxpucihal_ctrl.p_uwb_stack_cback != NULL) { in phNxpUciHal_client_thread()
171 (*nxpucihal_ctrl.p_uwb_stack_cback)(HAL_UWB_OPEN_CPLT_EVT, in phNxpUciHal_client_thread()
180 if (nxpucihal_ctrl.p_uwb_stack_cback != NULL) { in phNxpUciHal_client_thread()
182 (*nxpucihal_ctrl.p_uwb_stack_cback)(HAL_UWB_CLOSE_CPLT_EVT, in phNxpUciHal_client_thread()
192 if (nxpucihal_ctrl.p_uwb_stack_cback != NULL) { in phNxpUciHal_client_thread()
194 (*nxpucihal_ctrl.p_uwb_stack_cback)(HAL_UWB_INIT_CPLT_EVT, in phNxpUciHal_client_thread()
203 if (nxpucihal_ctrl.p_uwb_stack_cback != NULL) { in phNxpUciHal_client_thread()
205 (*nxpucihal_ctrl.p_uwb_stack_cback)(HAL_UWB_ERROR_EVT, in phNxpUciHal_client_thread()
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DphNxpUciHal_ext.cc41 extern phNxpUciHal_Control_t nxpucihal_ctrl;
88 if (phNxpUciHal_init_cb_data(&nxpucihal_ctrl.ext_cb_data, NULL) != UWBSTATUS_SUCCESS) { in phNxpUciHal_process_ext_cmd_rsp()
99 nxpucihal_ctrl.ext_cb_data.status = UWBSTATUS_FAILED; in phNxpUciHal_process_ext_cmd_rsp()
100 nxpucihal_ctrl.ext_cb_waiting = true; in phNxpUciHal_process_ext_cmd_rsp()
110 if (nxpucihal_ctrl.hal_parse_enabled) { in phNxpUciHal_process_ext_cmd_rsp()
116 phNxpUciHal_sem_timed_wait_msec(&nxpucihal_ctrl.ext_cb_data, HAL_EXTNS_WRITE_RSP_TIMEOUT_MS); in phNxpUciHal_process_ext_cmd_rsp()
118 nxpucihal_ctrl.ext_cb_waiting = false; in phNxpUciHal_process_ext_cmd_rsp()
120 switch (nxpucihal_ctrl.ext_cb_data.status) { in phNxpUciHal_process_ext_cmd_rsp()
130 status = nxpucihal_ctrl.ext_cb_data.status; in phNxpUciHal_process_ext_cmd_rsp()
136 NXPLOG_UCIHAL_E("Failed to process cmd/rsp 0x%x", nxpucihal_ctrl.ext_cb_data.status); in phNxpUciHal_process_ext_cmd_rsp()
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DphNxpUciHal.h136 #define HAL_ENABLE_EXT() (nxpucihal_ctrl.hal_ext_enabled = 1)
137 #define HAL_DISABLE_EXT() (nxpucihal_ctrl.hal_ext_enabled = 0)
DsessionTrack.cc13 extern phNxpUciHal_Control_t nxpucihal_ctrl;
224 phNxpUciHal_Runtime_Settings_t *rt_set = &nxpucihal_ctrl.rt_settings; in OnCountryCodeChanged()
/hardware/nxp/uwb/halimpl/hal/sr200/
DphNxpUciHal_LC.cc42 extern phNxpUciHal_Control_t nxpucihal_ctrl;
75 if (nxpucihal_ctrl.p_uwb_stack_cback != NULL) {
77 …if ((nxpucihal_ctrl.p_uwb_stack_data_cback != NULL) && (nxpucihal_lcfwdl_ctrl.rcv_data_len <= UCI_…
83 …(*nxpucihal_ctrl.p_uwb_stack_data_cback)(nxpucihal_lcfwdl_ctrl.rcv_data_len, nxpucihal_lcfwdl_ctrl…
87 if (nxpucihal_ctrl.p_uwb_stack_cback != NULL) {
89 …if ((nxpucihal_ctrl.p_uwb_stack_data_cback != NULL) && (nxpucihal_lcfwdl_ctrl.rcv_data_len <= UCI_…
93 …(*nxpucihal_ctrl.p_uwb_stack_data_cback)(nxpucihal_lcfwdl_ctrl.rcv_data_len, nxpucihal_lcfwdl_ctrl…
354 nxpucihal_lcfwdl_ctrl.rcv_data_len = nxpucihal_ctrl.rx_data_len;
355 …memcpy(&nxpucihal_lcfwdl_ctrl.rcv_data[0], nxpucihal_ctrl.p_rx_data, nxpucihal_lcfwdl_ctrl.rcv_dat…
377 if (phNxpUciHal_init_cb_data(&nxpucihal_ctrl.dev_status_ntf_wait, NULL) !=
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DNxpUwbChipSr200.cc14 extern phNxpUciHal_Control_t nxpucihal_ctrl;
66 if (nxpucihal_ctrl.fw_boot_mode == USER_FW_BOOT_MODE) in check_binding_done()
99 nxpucihal_ctrl.fw_dwnld_mode = true; in chip_init()
/hardware/nxp/uwb/halimpl/hal/sr1xx/
DNxpUwbChipSr1xx.cc15 extern phNxpUciHal_Control_t nxpucihal_ctrl;
27 nxpucihal_ctrl.rx_data_len = 5; in report_binding_status()
28 if (nxpucihal_ctrl.p_uwb_stack_data_cback != NULL) { in report_binding_status()
29 (*nxpucihal_ctrl.p_uwb_stack_data_cback)(data_len, buffer); in report_binding_status()
58 NXPLOG_UCIHAL_E("Otp read: bad status=0x%x", nxpucihal_ctrl.p_rx_data[4]); in otp_read_data()
314 nxpucihal_ctrl.isSkipPacket = 1; in onGenericErrorNtf()
340 if (nxpucihal_ctrl.fw_boot_mode == USER_FW_BOOT_MODE) in check_binding()
414 nxpucihal_ctrl.fw_dwnld_mode = true; in chip_init()
498 if (nxpucihal_ctrl.fw_version.major_version == 0xFF) { in extra_group_delay()
503 else if (nxpucihal_ctrl.fw_version.major_version >= 0x50) { in extra_group_delay()
/hardware/nxp/uwb/halimpl/tml/
DphTmlUwb_spi.cc32 extern phNxpUciHal_Control_t nxpucihal_ctrl;
134 …} else if((nxpucihal_ctrl.fw_dwnld_mode) && ((0xFF == pBuffer[0]) || ((0x00 == pBuffer[0]) && (0x0… in phTmlUwb_spi_read()
DphOsalUwb_Timer.cc27 extern phNxpUciHal_Control_t nxpucihal_ctrl;
367 nxpucihal_ctrl.gDrvCfg.pClientMq->send(msg); in phOsalUwb_Timer_Expired()
DphTmlUwb.cc25 extern phNxpUciHal_Control_t nxpucihal_ctrl;