1 /******************************************************************************
2 *
3 * Copyright 1999-2012 Broadcom Corporation
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 ******************************************************************************/
18
19 /******************************************************************************
20 *
21 * This file contains function of the HCIC unit to format and send HCI
22 * commands.
23 *
24 ******************************************************************************/
25
26 #include <base/functional/bind.h>
27 #include <base/functional/callback_forward.h>
28 #include <string.h>
29
30 #include "device/include/esco_parameters.h"
31 #include "hcidefs.h"
32 #include "hcimsgs.h"
33 #include "internal_include/bt_target.h"
34 #include "main/shim/acl_api.h"
35 #include "osi/include/allocator.h"
36 #include "stack/include/bt_dev_class.h"
37 #include "stack/include/bt_hdr.h"
38 #include "stack/include/bt_lap.h"
39 #include "stack/include/bt_octets.h"
40 #include "stack/include/bt_types.h"
41 #include "stack/include/btu_hcif.h"
42 #include "types/raw_address.h"
43
44 /* Message by message.... */
45
46 #define HCIC_PARAM_SIZE_INQUIRY 5
47
48 #define HCIC_INQ_INQ_LAP_OFF 0
49 #define HCIC_INQ_DUR_OFF 3
50 #define HCIC_INQ_RSP_CNT_OFF 4
51
52 /* Periodic Inquiry Mode */
53 #define HCIC_PARAM_SIZE_PER_INQ_MODE 9
54
55 #define HCI_PER_INQ_MAX_INTRVL_OFF 0
56 #define HCI_PER_INQ_MIN_INTRVL_OFF 2
57 #define HCI_PER_INQ_INQ_LAP_OFF 4
58 #define HCI_PER_INQ_DURATION_OFF 7
59 #define HCI_PER_INQ_RSP_CNT_OFF 8
60 /* Periodic Inquiry Mode */
61
62 /* Exit Periodic Inquiry Mode */
63 #define HCIC_PARAM_SIZE_EXIT_PER_INQ 0
64
65 /* Create Connection */
66 #define HCIC_PARAM_SIZE_CREATE_CONN 13
67
68 #define HCIC_CR_CONN_BD_ADDR_OFF 0
69 #define HCIC_CR_CONN_PKT_TYPES_OFF 6
70 #define HCIC_CR_CONN_REP_MODE_OFF 8
71 #define HCIC_CR_CONN_PAGE_SCAN_MODE_OFF 9
72 #define HCIC_CR_CONN_CLK_OFF_OFF 10
73 #define HCIC_CR_CONN_ALLOW_SWITCH_OFF 12
74 /* Create Connection */
75
76 /* Disconnect */
77 #define HCIC_PARAM_SIZE_DISCONNECT 3
78
79 #define HCI_DISC_HANDLE_OFF 0
80 #define HCI_DISC_REASON_OFF 2
81 /* Disconnect */
82
83 /* Add SCO Connection */
84 #define HCIC_PARAM_SIZE_ADD_SCO_CONN 4
85
86 #define HCI_ADD_SCO_HANDLE_OFF 0
87 #define HCI_ADD_SCO_PACKET_TYPES_OFF 2
88 /* Add SCO Connection */
89
90 /* Create Connection Cancel */
91 #define HCIC_PARAM_SIZE_CREATE_CONN_CANCEL 6
92
93 #define HCIC_CR_CONN_CANCEL_BD_ADDR_OFF 0
94 /* Create Connection Cancel */
95
96 /* Accept Connection Request */
97 #define HCIC_PARAM_SIZE_ACCEPT_CONN 7
98
99 #define HCI_ACC_CONN_BD_ADDR_OFF 0
100 #define HCI_ACC_CONN_ROLE_OFF 6
101 /* Accept Connection Request */
102
103 /* Reject Connection Request */
104 #define HCIC_PARAM_SIZE_REJECT_CONN 7
105
106 #define HCI_REJ_CONN_BD_ADDR_OFF 0
107 #define HCI_REJ_CONN_REASON_OFF 6
108 /* Reject Connection Request */
109
110 /* Link Key Request Reply */
111 #define HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY 22
112
113 #define HCI_LINK_KEY_REPLY_BD_ADDR_OFF 0
114 #define HCI_LINK_KEY_REPLY_LINK_KEY_OFF 6
115 /* Link Key Request Reply */
116
117 /* Link Key Request Neg Reply */
118 #define HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY 6
119
120 #define HCI_LINK_KEY_NEG_REP_BD_ADR_OFF 0
121 /* Link Key Request Neg Reply */
122
123 /* PIN Code Request Reply */
124 #define HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY 23
125
126 #define HCI_PIN_CODE_REPLY_BD_ADDR_OFF 0
127 #define HCI_PIN_CODE_REPLY_PIN_LEN_OFF 6
128 #define HCI_PIN_CODE_REPLY_PIN_CODE_OFF 7
129 /* PIN Code Request Reply */
130
131 /* Link Key Request Neg Reply */
132 #define HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY 6
133
134 #define HCI_PIN_CODE_NEG_REP_BD_ADR_OFF 0
135 /* Link Key Request Neg Reply */
136
137 /* Change Connection Type */
138 #define HCIC_PARAM_SIZE_CHANGE_CONN_TYPE 4
139
140 #define HCI_CHNG_PKT_TYPE_HANDLE_OFF 0
141 #define HCI_CHNG_PKT_TYPE_PKT_TYPE_OFF 2
142 /* Change Connection Type */
143
144 #define HCIC_PARAM_SIZE_CMD_HANDLE 2
145
146 #define HCI_CMD_HANDLE_HANDLE_OFF 0
147
148 /* Set Connection Encryption */
149 #define HCIC_PARAM_SIZE_SET_CONN_ENCRYPT 3
150
151 #define HCI_SET_ENCRYPT_HANDLE_OFF 0
152 #define HCI_SET_ENCRYPT_ENABLE_OFF 2
153 /* Set Connection Encryption */
154
155 /* Remote Name Request */
156 #define HCIC_PARAM_SIZE_RMT_NAME_REQ 10
157
158 #define HCI_RMT_NAME_BD_ADDR_OFF 0
159 #define HCI_RMT_NAME_REP_MODE_OFF 6
160 #define HCI_RMT_NAME_PAGE_SCAN_MODE_OFF 7
161 #define HCI_RMT_NAME_CLK_OFF_OFF 8
162 /* Remote Name Request */
163
164 /* Remote Name Request Cancel */
165 #define HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL 6
166
167 #define HCI_RMT_NAME_CANCEL_BD_ADDR_OFF 0
168 /* Remote Name Request Cancel */
169
170 /* Remote Extended Features */
171 #define HCIC_PARAM_SIZE_RMT_EXT_FEATURES 3
172
173 #define HCI_RMT_EXT_FEATURES_HANDLE_OFF 0
174 #define HCI_RMT_EXT_FEATURES_PAGE_NUM_OFF 2
175 /* Remote Extended Features */
176
177 #define HCIC_PARAM_SIZE_SETUP_ESCO 17
178
179 #define HCI_SETUP_ESCO_HANDLE_OFF 0
180 #define HCI_SETUP_ESCO_TX_BW_OFF 2
181 #define HCI_SETUP_ESCO_RX_BW_OFF 6
182 #define HCI_SETUP_ESCO_MAX_LAT_OFF 10
183 #define HCI_SETUP_ESCO_VOICE_OFF 12
184 #define HCI_SETUP_ESCO_RETRAN_EFF_OFF 14
185 #define HCI_SETUP_ESCO_PKT_TYPES_OFF 15
186
187 #define HCIC_PARAM_SIZE_ACCEPT_ESCO 21
188
189 #define HCI_ACCEPT_ESCO_BDADDR_OFF 0
190 #define HCI_ACCEPT_ESCO_TX_BW_OFF 6
191 #define HCI_ACCEPT_ESCO_RX_BW_OFF 10
192 #define HCI_ACCEPT_ESCO_MAX_LAT_OFF 14
193 #define HCI_ACCEPT_ESCO_VOICE_OFF 16
194 #define HCI_ACCEPT_ESCO_RETRAN_EFF_OFF 18
195 #define HCI_ACCEPT_ESCO_PKT_TYPES_OFF 19
196
197 #define HCIC_PARAM_SIZE_REJECT_ESCO 7
198
199 #define HCI_REJECT_ESCO_BDADDR_OFF 0
200 #define HCI_REJECT_ESCO_REASON_OFF 6
201
202 /* Hold Mode */
203 #define HCIC_PARAM_SIZE_HOLD_MODE 6
204
205 #define HCI_HOLD_MODE_HANDLE_OFF 0
206 #define HCI_HOLD_MODE_MAX_PER_OFF 2
207 #define HCI_HOLD_MODE_MIN_PER_OFF 4
208 /* Hold Mode */
209
210 /* Sniff Mode */
211 #define HCIC_PARAM_SIZE_SNIFF_MODE 10
212
213 #define HCI_SNIFF_MODE_HANDLE_OFF 0
214 #define HCI_SNIFF_MODE_MAX_PER_OFF 2
215 #define HCI_SNIFF_MODE_MIN_PER_OFF 4
216 #define HCI_SNIFF_MODE_ATTEMPT_OFF 6
217 #define HCI_SNIFF_MODE_TIMEOUT_OFF 8
218 /* Sniff Mode */
219
220 /* Park Mode */
221 #define HCIC_PARAM_SIZE_PARK_MODE 6
222
223 #define HCI_PARK_MODE_HANDLE_OFF 0
224 #define HCI_PARK_MODE_MAX_PER_OFF 2
225 #define HCI_PARK_MODE_MIN_PER_OFF 4
226 /* Park Mode */
227
228 /* QoS Setup */
229 #define HCIC_PARAM_SIZE_QOS_SETUP 20
230
231 #define HCI_QOS_HANDLE_OFF 0
232 #define HCI_QOS_FLAGS_OFF 2
233 #define HCI_QOS_SERVICE_TYPE_OFF 3
234 #define HCI_QOS_TOKEN_RATE_OFF 4
235 #define HCI_QOS_PEAK_BANDWIDTH_OFF 8
236 #define HCI_QOS_LATENCY_OFF 12
237 #define HCI_QOS_DELAY_VAR_OFF 16
238 /* QoS Setup */
239
240 #define HCIC_PARAM_SIZE_SWITCH_ROLE 7
241
242 #define HCI_SWITCH_BD_ADDR_OFF 0
243 #define HCI_SWITCH_ROLE_OFF 6
244 /* Switch Role Request */
245
246 /* Write Policy Settings */
247 #define HCIC_PARAM_SIZE_WRITE_POLICY_SET 4
248
249 #define HCI_WRITE_POLICY_HANDLE_OFF 0
250 #define HCI_WRITE_POLICY_SETTINGS_OFF 2
251 /* Write Policy Settings */
252
253 /* Write Default Policy Settings */
254 #define HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET 2
255
256 #define HCI_WRITE_DEF_POLICY_SETTINGS_OFF 0
257 /* Write Default Policy Settings */
258
259 #define HCIC_PARAM_SIZE_SNIFF_SUB_RATE 8
260
261 #define HCI_SNIFF_SUB_RATE_HANDLE_OFF 0
262 #define HCI_SNIFF_SUB_RATE_MAX_LAT_OFF 2
263 #define HCI_SNIFF_SUB_RATE_MIN_REM_LAT_OFF 4
264 #define HCI_SNIFF_SUB_RATE_MIN_LOC_LAT_OFF 6
265 /* Sniff Subrating */
266
267 /* Extended Inquiry Response */
268 #define HCIC_PARAM_SIZE_EXT_INQ_RESP 241
269
270 #define HCIC_EXT_INQ_RESP_FEC_OFF 0
271 #define HCIC_EXT_INQ_RESP_RESPONSE 1
272 /* IO Capabilities Response */
273 #define HCIC_PARAM_SIZE_IO_CAP_RESP 9
274
275 #define HCI_IO_CAP_BD_ADDR_OFF 0
276 #define HCI_IO_CAPABILITY_OFF 6
277 #define HCI_IO_CAP_OOB_DATA_OFF 7
278 #define HCI_IO_CAP_AUTH_REQ_OFF 8
279
280 /* IO Capabilities Req Neg Reply */
281 #define HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY 7
282
283 #define HCI_IO_CAP_NR_BD_ADDR_OFF 0
284 #define HCI_IO_CAP_NR_ERR_CODE 6
285
286 /* Read Local OOB Data */
287 #define HCIC_PARAM_SIZE_R_LOCAL_OOB 0
288
289 /* Read Local OOB Extended Data */
290 #define HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED 0
291
292 #define HCIC_PARAM_SIZE_UCONF_REPLY 6
293
294 #define HCI_USER_CONF_BD_ADDR_OFF 0
295
296 #define HCIC_PARAM_SIZE_U_PKEY_REPLY 10
297
298 #define HCI_USER_PASSKEY_BD_ADDR_OFF 0
299 #define HCI_USER_PASSKEY_VALUE_OFF 6
300
301 #define HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY 6
302
303 #define HCI_USER_PASSKEY_NEG_BD_ADDR_OFF 0
304
305 /* Remote OOB Data Request Reply */
306 #define HCIC_PARAM_SIZE_REM_OOB_REPLY 38
307
308 #define HCI_REM_OOB_DATA_BD_ADDR_OFF 0
309 #define HCI_REM_OOB_DATA_C_OFF 6
310 #define HCI_REM_OOB_DATA_R_OFF 22
311
312 /* Remote OOB Data Request Negative Reply */
313 #define HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY 6
314
315 #define HCI_REM_OOB_DATA_NEG_BD_ADDR_OFF 0
316
317 /* Read Tx Power Level */
318 #define HCIC_PARAM_SIZE_R_TX_POWER 0
319
320 /* Read Default Erroneous Data Reporting */
321 #define HCIC_PARAM_SIZE_R_ERR_DATA_RPT 0
322
323 #define HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF 7
324
325 #define HCI_SEND_KEYPRESS_NOTIF_BD_ADDR_OFF 0
326 #define HCI_SEND_KEYPRESS_NOTIF_NOTIF_OFF 6
327
328 /**** end of Simple Pairing Commands ****/
329
330 #define HCIC_PARAM_SIZE_SET_EVT_FILTER 9
331
332 #define HCI_FILT_COND_FILT_TYPE_OFF 0
333 #define HCI_FILT_COND_COND_TYPE_OFF 1
334 #define HCI_FILT_COND_FILT_OFF 2
335 /* Set Event Filter */
336
337 /* Delete Stored Key */
338 #define HCIC_PARAM_SIZE_DELETE_STORED_KEY 7
339
340 #define HCI_DELETE_KEY_BD_ADDR_OFF 0
341 #define HCI_DELETE_KEY_ALL_FLAG_OFF 6
342 /* Delete Stored Key */
343
344 /* Change Local Name */
345 #define HCIC_PARAM_SIZE_CHANGE_NAME BD_NAME_LEN
346
347 #define HCI_CHANGE_NAME_NAME_OFF 0
348 /* Change Local Name */
349
350 #define HCIC_PARAM_SIZE_READ_CMD 0
351
352 #define HCIC_PARAM_SIZE_WRITE_PARAM1 1
353
354 #define HCIC_WRITE_PARAM1_PARAM_OFF 0
355
356 #define HCIC_PARAM_SIZE_WRITE_PARAM2 2
357
358 #define HCIC_WRITE_PARAM2_PARAM_OFF 0
359
360 #define HCIC_PARAM_SIZE_WRITE_PARAM3 3
361
362 #define HCIC_WRITE_PARAM3_PARAM_OFF 0
363
364 #define HCIC_PARAM_SIZE_SET_AFH_CHANNELS 10
365
366 #define HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN 59
367 #define HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN 63
368
369 #define HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG 4
370
371 #define HCI_SCAN_CFG_INTERVAL_OFF 0
372 #define HCI_SCAN_CFG_WINDOW_OFF 2
373 /* Write Page Scan Activity */
374
375 /* Write Inquiry Scan Activity */
376 #define HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG 4
377
378 #define HCI_SCAN_CFG_INTERVAL_OFF 0
379 #define HCI_SCAN_CFG_WINDOW_OFF 2
380 /* Write Inquiry Scan Activity */
381
382 /* Host Controller to Host flow control */
383 #define HCI_HOST_FLOW_CTRL_OFF 0
384 #define HCI_HOST_FLOW_CTRL_ACL_ON 1
385 #define HCI_HOST_FLOW_CTRL_SCO_ON 2
386 #define HCI_HOST_FLOW_CTRL_BOTH_ON 3
387
388 #define HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT 4
389
390 #define HCI_FLUSH_TOUT_HANDLE_OFF 0
391 #define HCI_FLUSH_TOUT_TOUT_OFF 2
392
393 #define HCIC_PARAM_SIZE_READ_TX_POWER 3
394
395 #define HCI_READ_TX_POWER_HANDLE_OFF 0
396 #define HCI_READ_TX_POWER_TYPE_OFF 2
397
398 /* Read transmit power level parameter */
399 #define HCI_READ_CURRENT 0x00
400 #define HCI_READ_MAXIMUM 0x01
401
402 #define HCIC_PARAM_SIZE_NUM_PKTS_DONE_SIZE sizeof(btmsg_hcic_num_pkts_done_t)
403
404 #define MAX_DATA_HANDLES 10
405
406 #define HCI_PKTS_DONE_NUM_HANDLES_OFF 0
407 #define HCI_PKTS_DONE_HANDLE_OFF 1
408 #define HCI_PKTS_DONE_NUM_PKTS_OFF 3
409
410 #define HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT 4
411
412 #define HCI_LINK_SUPER_TOUT_HANDLE_OFF 0
413 #define HCI_LINK_SUPER_TOUT_TOUT_OFF 2
414 /* Write Link Supervision Timeout */
415
416 #define MAX_IAC_LAPS 0x40
417
418 #define HCI_WRITE_IAC_LAP_NUM_OFF 0
419 #define HCI_WRITE_IAC_LAP_LAP_OFF 1
420 /* Write Current IAC LAP */
421
422 #define HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH 3
423
424 /*******************************************************************************
425 * BLE Commands
426 * Note: "local_controller_id" is for transport, not counted in HCI
427 * message size
428 ******************************************************************************/
429 #define HCIC_BLE_RAND_DI_SIZE 8
430 #define HCIC_BLE_IRK_SIZE 16
431
432 #define HCIC_PARAM_SIZE_SET_USED_FEAT_CMD 8
433 #define HCIC_PARAM_SIZE_WRITE_RANDOM_ADDR_CMD 6
434 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_PARAMS 15
435 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_RSP 31
436 #define HCIC_PARAM_SIZE_WRITE_ADV_ENABLE 1
437 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_PARAM 7
438 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_ENABLE 2
439 #define HCIC_PARAM_SIZE_BLE_CREATE_LL_CONN 25
440 #define HCIC_PARAM_SIZE_BLE_CREATE_CONN_CANCEL 0
441 #define HCIC_PARAM_SIZE_CLEAR_ACCEPTLIST 0
442 #define HCIC_PARAM_SIZE_ADD_ACCEPTLIST 7
443 #define HCIC_PARAM_SIZE_REMOVE_ACCEPTLIST 7
444 #define HCIC_PARAM_SIZE_BLE_UPD_LL_CONN_PARAMS 14
445 #define HCIC_PARAM_SIZE_SET_HOST_CHNL_CLASS 5
446 #define HCIC_PARAM_SIZE_READ_CHNL_MAP 2
447 #define HCIC_PARAM_SIZE_BLE_READ_REMOTE_FEAT 2
448 #define HCIC_PARAM_SIZE_BLE_ENCRYPT 32
449 #define HCIC_PARAM_SIZE_WRITE_LE_HOST_SUPPORTED 2
450
451 #define HCIC_BLE_RAND_DI_SIZE 8
452 #define HCIC_BLE_ENCRYPT_KEY_SIZE 16
453 #define HCIC_PARAM_SIZE_BLE_START_ENC \
454 (4 + HCIC_BLE_RAND_DI_SIZE + HCIC_BLE_ENCRYPT_KEY_SIZE)
455 #define HCIC_PARAM_SIZE_LTK_REQ_REPLY (2 + HCIC_BLE_ENCRYPT_KEY_SIZE)
456 #define HCIC_PARAM_SIZE_LTK_REQ_NEG_REPLY 2
457 #define HCIC_BLE_CHNL_MAP_SIZE 5
458 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_DATA 31
459
460 #define HCIC_PARAM_SIZE_BLE_ADD_DEV_RESOLVING_LIST (7 + HCIC_BLE_IRK_SIZE * 2)
461 #define HCIC_PARAM_SIZE_BLE_RM_DEV_RESOLVING_LIST 7
462 #define HCIC_PARAM_SIZE_BLE_SET_PRIVACY_MODE 8
463 #define HCIC_PARAM_SIZE_BLE_CLEAR_RESOLVING_LIST 0
464 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVING_LIST_SIZE 0
465 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_PEER 7
466 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_LOCAL 7
467 #define HCIC_PARAM_SIZE_BLE_SET_ADDR_RESOLUTION_ENABLE 1
468 #define HCIC_PARAM_SIZE_BLE_SET_RAND_PRIV_ADDR_TIMOUT 2
469
470 #define HCIC_PARAM_SIZE_BLE_READ_PHY 2
471 #define HCIC_PARAM_SIZE_BLE_SET_DEFAULT_PHY 3
472 #define HCIC_PARAM_SIZE_BLE_SET_PHY 7
473 #define HCIC_PARAM_SIZE_BLE_ENH_RX_TEST 3
474 #define HCIC_PARAM_SIZE_BLE_ENH_TX_TEST 4
475
476 #define HCIC_PARAM_SIZE_BLE_SET_DATA_LENGTH 6
477 #define HCIC_PARAM_SIZE_BLE_WRITE_EXTENDED_SCAN_PARAM 11
478
479 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_REPLY 14
480 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_NEG_REPLY 3
481
btsnd_hcic_disconnect(uint16_t handle,uint8_t reason)482 static void btsnd_hcic_disconnect(uint16_t handle, uint8_t reason) {
483 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
484 uint8_t* pp = (uint8_t*)(p + 1);
485
486 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DISCONNECT;
487 p->offset = 0;
488
489 UINT16_TO_STREAM(pp, HCI_DISCONNECT);
490 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DISCONNECT);
491 UINT16_TO_STREAM(pp, handle);
492 UINT8_TO_STREAM(pp, reason);
493
494 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
495 }
496
btsnd_hcic_add_SCO_conn(uint16_t handle,uint16_t packet_types)497 void btsnd_hcic_add_SCO_conn(uint16_t handle, uint16_t packet_types) {
498 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
499 uint8_t* pp = (uint8_t*)(p + 1);
500
501 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ADD_SCO_CONN;
502 p->offset = 0;
503
504 UINT16_TO_STREAM(pp, HCI_ADD_SCO_CONNECTION);
505 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ADD_SCO_CONN);
506
507 UINT16_TO_STREAM(pp, handle);
508 UINT16_TO_STREAM(pp, packet_types);
509
510 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
511 }
512
btsnd_hcic_create_conn_cancel(const RawAddress & dest)513 void btsnd_hcic_create_conn_cancel(const RawAddress& dest) {
514 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
515 uint8_t* pp = (uint8_t*)(p + 1);
516
517 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN_CANCEL;
518 p->offset = 0;
519
520 UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION_CANCEL);
521 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN_CANCEL);
522
523 BDADDR_TO_STREAM(pp, dest);
524
525 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
526 }
527
btsnd_hcic_reject_conn(const RawAddress & dest,uint8_t reason)528 void btsnd_hcic_reject_conn(const RawAddress& dest, uint8_t reason) {
529 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
530 uint8_t* pp = (uint8_t*)(p + 1);
531
532 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_CONN;
533 p->offset = 0;
534
535 UINT16_TO_STREAM(pp, HCI_REJECT_CONNECTION_REQUEST);
536 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_CONN);
537
538 BDADDR_TO_STREAM(pp, dest);
539 UINT8_TO_STREAM(pp, reason);
540
541 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
542 }
543
btsnd_hcic_link_key_req_reply(const RawAddress & bd_addr,const LinkKey & link_key)544 void btsnd_hcic_link_key_req_reply(const RawAddress& bd_addr,
545 const LinkKey& link_key) {
546 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
547 uint8_t* pp = (uint8_t*)(p + 1);
548
549 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY;
550 p->offset = 0;
551
552 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_REPLY);
553 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY);
554
555 BDADDR_TO_STREAM(pp, bd_addr);
556 ARRAY16_TO_STREAM(pp, link_key.data());
557
558 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
559 }
560
btsnd_hcic_link_key_neg_reply(const RawAddress & bd_addr)561 void btsnd_hcic_link_key_neg_reply(const RawAddress& bd_addr) {
562 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
563 uint8_t* pp = (uint8_t*)(p + 1);
564
565 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY;
566 p->offset = 0;
567
568 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_NEG_REPLY);
569 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY);
570
571 BDADDR_TO_STREAM(pp, bd_addr);
572
573 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
574 }
575
btsnd_hcic_pin_code_req_reply(const RawAddress & bd_addr,uint8_t pin_code_len,PIN_CODE pin_code)576 void btsnd_hcic_pin_code_req_reply(const RawAddress& bd_addr,
577 uint8_t pin_code_len, PIN_CODE pin_code) {
578 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
579 uint8_t* pp = (uint8_t*)(p + 1);
580 int i;
581
582 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY;
583 p->offset = 0;
584
585 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_REPLY);
586 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY);
587
588 BDADDR_TO_STREAM(pp, bd_addr);
589 UINT8_TO_STREAM(pp, pin_code_len);
590
591 for (i = 0; i < pin_code_len; i++) *pp++ = *pin_code++;
592
593 for (; i < PIN_CODE_LEN; i++) *pp++ = 0;
594
595 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
596 }
597
btsnd_hcic_pin_code_neg_reply(const RawAddress & bd_addr)598 void btsnd_hcic_pin_code_neg_reply(const RawAddress& bd_addr) {
599 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
600 uint8_t* pp = (uint8_t*)(p + 1);
601
602 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY;
603 p->offset = 0;
604
605 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_NEG_REPLY);
606 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY);
607
608 BDADDR_TO_STREAM(pp, bd_addr);
609
610 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
611 }
612
btsnd_hcic_change_conn_type(uint16_t handle,uint16_t packet_types)613 void btsnd_hcic_change_conn_type(uint16_t handle, uint16_t packet_types) {
614 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
615 uint8_t* pp = (uint8_t*)(p + 1);
616
617 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_CONN_TYPE;
618 p->offset = 0;
619
620 UINT16_TO_STREAM(pp, HCI_CHANGE_CONN_PACKET_TYPE);
621 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_CONN_TYPE);
622
623 UINT16_TO_STREAM(pp, handle);
624 UINT16_TO_STREAM(pp, packet_types);
625
626 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
627 }
628
btsnd_hcic_auth_request(uint16_t handle)629 void btsnd_hcic_auth_request(uint16_t handle) {
630 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
631 uint8_t* pp = (uint8_t*)(p + 1);
632
633 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
634 p->offset = 0;
635
636 UINT16_TO_STREAM(pp, HCI_AUTHENTICATION_REQUESTED);
637 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
638
639 UINT16_TO_STREAM(pp, handle);
640
641 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
642 }
643
btsnd_hcic_set_conn_encrypt(uint16_t handle,bool enable)644 void btsnd_hcic_set_conn_encrypt(uint16_t handle, bool enable) {
645 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
646 uint8_t* pp = (uint8_t*)(p + 1);
647
648 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SET_CONN_ENCRYPT;
649 p->offset = 0;
650
651 UINT16_TO_STREAM(pp, HCI_SET_CONN_ENCRYPTION);
652 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SET_CONN_ENCRYPT);
653
654 UINT16_TO_STREAM(pp, handle);
655 UINT8_TO_STREAM(pp, enable);
656
657 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
658 }
659
btsnd_hcic_rmt_ext_features(uint16_t handle,uint8_t page_num)660 void btsnd_hcic_rmt_ext_features(uint16_t handle, uint8_t page_num) {
661 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
662 uint8_t* pp = (uint8_t*)(p + 1);
663
664 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_EXT_FEATURES;
665 p->offset = 0;
666
667 UINT16_TO_STREAM(pp, HCI_READ_RMT_EXT_FEATURES);
668 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_EXT_FEATURES);
669
670 UINT16_TO_STREAM(pp, handle);
671 UINT8_TO_STREAM(pp, page_num);
672
673 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
674 }
675
btsnd_hcic_rmt_ver_req(uint16_t handle)676 void btsnd_hcic_rmt_ver_req(uint16_t handle) {
677 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
678 uint8_t* pp = (uint8_t*)(p + 1);
679
680 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
681 p->offset = 0;
682
683 UINT16_TO_STREAM(pp, HCI_READ_RMT_VERSION_INFO);
684 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
685
686 UINT16_TO_STREAM(pp, handle);
687
688 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
689 }
690
btsnd_hcic_read_rmt_clk_offset(uint16_t handle)691 void btsnd_hcic_read_rmt_clk_offset(uint16_t handle) {
692 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
693 uint8_t* pp = (uint8_t*)(p + 1);
694
695 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
696 p->offset = 0;
697
698 UINT16_TO_STREAM(pp, HCI_READ_RMT_CLOCK_OFFSET);
699 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
700
701 UINT16_TO_STREAM(pp, handle);
702
703 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
704 }
705
btsnd_hcic_setup_esco_conn(uint16_t handle,uint32_t transmit_bandwidth,uint32_t receive_bandwidth,uint16_t max_latency,uint16_t voice,uint8_t retrans_effort,uint16_t packet_types)706 void btsnd_hcic_setup_esco_conn(uint16_t handle, uint32_t transmit_bandwidth,
707 uint32_t receive_bandwidth,
708 uint16_t max_latency, uint16_t voice,
709 uint8_t retrans_effort, uint16_t packet_types) {
710 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
711 uint8_t* pp = (uint8_t*)(p + 1);
712
713 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SETUP_ESCO;
714 p->offset = 0;
715
716 UINT16_TO_STREAM(pp, HCI_SETUP_ESCO_CONNECTION);
717 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SETUP_ESCO);
718
719 UINT16_TO_STREAM(pp, handle);
720 UINT32_TO_STREAM(pp, transmit_bandwidth);
721 UINT32_TO_STREAM(pp, receive_bandwidth);
722 UINT16_TO_STREAM(pp, max_latency);
723 UINT16_TO_STREAM(pp, voice);
724 UINT8_TO_STREAM(pp, retrans_effort);
725 UINT16_TO_STREAM(pp, packet_types);
726
727 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
728 }
729
btsnd_hcic_accept_esco_conn(const RawAddress & bd_addr,uint32_t transmit_bandwidth,uint32_t receive_bandwidth,uint16_t max_latency,uint16_t content_fmt,uint8_t retrans_effort,uint16_t packet_types)730 void btsnd_hcic_accept_esco_conn(const RawAddress& bd_addr,
731 uint32_t transmit_bandwidth,
732 uint32_t receive_bandwidth,
733 uint16_t max_latency, uint16_t content_fmt,
734 uint8_t retrans_effort,
735 uint16_t packet_types) {
736 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
737 uint8_t* pp = (uint8_t*)(p + 1);
738
739 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_ESCO;
740 p->offset = 0;
741
742 UINT16_TO_STREAM(pp, HCI_ACCEPT_ESCO_CONNECTION);
743 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_ESCO);
744
745 BDADDR_TO_STREAM(pp, bd_addr);
746 UINT32_TO_STREAM(pp, transmit_bandwidth);
747 UINT32_TO_STREAM(pp, receive_bandwidth);
748 UINT16_TO_STREAM(pp, max_latency);
749 UINT16_TO_STREAM(pp, content_fmt);
750 UINT8_TO_STREAM(pp, retrans_effort);
751 UINT16_TO_STREAM(pp, packet_types);
752
753 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
754 }
755
btsnd_hcic_reject_esco_conn(const RawAddress & bd_addr,uint8_t reason)756 void btsnd_hcic_reject_esco_conn(const RawAddress& bd_addr, uint8_t reason) {
757 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
758 uint8_t* pp = (uint8_t*)(p + 1);
759
760 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_ESCO;
761 p->offset = 0;
762
763 UINT16_TO_STREAM(pp, HCI_REJECT_ESCO_CONNECTION);
764 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_ESCO);
765
766 BDADDR_TO_STREAM(pp, bd_addr);
767 UINT8_TO_STREAM(pp, reason);
768
769 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
770 }
771
btsnd_hcic_hold_mode(uint16_t handle,uint16_t max_hold_period,uint16_t min_hold_period)772 void btsnd_hcic_hold_mode(uint16_t handle, uint16_t max_hold_period,
773 uint16_t min_hold_period) {
774 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
775 uint8_t* pp = (uint8_t*)(p + 1);
776
777 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_HOLD_MODE;
778 p->offset = 0;
779
780 UINT16_TO_STREAM(pp, HCI_HOLD_MODE);
781 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_HOLD_MODE);
782
783 UINT16_TO_STREAM(pp, handle);
784 UINT16_TO_STREAM(pp, max_hold_period);
785 UINT16_TO_STREAM(pp, min_hold_period);
786
787 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
788 }
789
btsnd_hcic_sniff_mode(uint16_t handle,uint16_t max_sniff_period,uint16_t min_sniff_period,uint16_t sniff_attempt,uint16_t sniff_timeout)790 void btsnd_hcic_sniff_mode(uint16_t handle, uint16_t max_sniff_period,
791 uint16_t min_sniff_period, uint16_t sniff_attempt,
792 uint16_t sniff_timeout) {
793 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
794 uint8_t* pp = (uint8_t*)(p + 1);
795
796 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_MODE;
797 p->offset = 0;
798
799 UINT16_TO_STREAM(pp, HCI_SNIFF_MODE);
800 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_MODE);
801
802 UINT16_TO_STREAM(pp, handle);
803 UINT16_TO_STREAM(pp, max_sniff_period);
804 UINT16_TO_STREAM(pp, min_sniff_period);
805 UINT16_TO_STREAM(pp, sniff_attempt);
806 UINT16_TO_STREAM(pp, sniff_timeout);
807
808 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
809 }
810
btsnd_hcic_exit_sniff_mode(uint16_t handle)811 void btsnd_hcic_exit_sniff_mode(uint16_t handle) {
812 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
813 uint8_t* pp = (uint8_t*)(p + 1);
814
815 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
816 p->offset = 0;
817
818 UINT16_TO_STREAM(pp, HCI_EXIT_SNIFF_MODE);
819 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
820
821 UINT16_TO_STREAM(pp, handle);
822
823 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
824 }
825
btsnd_hcic_park_mode(uint16_t handle,uint16_t beacon_max_interval,uint16_t beacon_min_interval)826 void btsnd_hcic_park_mode(uint16_t handle, uint16_t beacon_max_interval,
827 uint16_t beacon_min_interval) {
828 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
829 uint8_t* pp = (uint8_t*)(p + 1);
830
831 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PARK_MODE;
832 p->offset = 0;
833
834 UINT16_TO_STREAM(pp, HCI_PARK_MODE);
835 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PARK_MODE);
836
837 UINT16_TO_STREAM(pp, handle);
838 UINT16_TO_STREAM(pp, beacon_max_interval);
839 UINT16_TO_STREAM(pp, beacon_min_interval);
840
841 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
842 }
843
btsnd_hcic_exit_park_mode(uint16_t handle)844 void btsnd_hcic_exit_park_mode(uint16_t handle) {
845 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
846 uint8_t* pp = (uint8_t*)(p + 1);
847
848 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
849 p->offset = 0;
850
851 UINT16_TO_STREAM(pp, HCI_EXIT_PARK_MODE);
852 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
853
854 UINT16_TO_STREAM(pp, handle);
855
856 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
857 }
858
btsnd_hcic_switch_role(const RawAddress & bd_addr,uint8_t role)859 static void btsnd_hcic_switch_role(const RawAddress& bd_addr, uint8_t role) {
860 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
861 uint8_t* pp = (uint8_t*)(p + 1);
862
863 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SWITCH_ROLE;
864 p->offset = 0;
865
866 UINT16_TO_STREAM(pp, HCI_SWITCH_ROLE);
867 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SWITCH_ROLE);
868
869 BDADDR_TO_STREAM(pp, bd_addr);
870 UINT8_TO_STREAM(pp, role);
871
872 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
873 }
874
btsnd_hcic_write_policy_set(uint16_t handle,uint16_t settings)875 void btsnd_hcic_write_policy_set(uint16_t handle, uint16_t settings) {
876 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
877 uint8_t* pp = (uint8_t*)(p + 1);
878
879 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_POLICY_SET;
880 p->offset = 0;
881 UINT16_TO_STREAM(pp, HCI_WRITE_POLICY_SETTINGS);
882 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_POLICY_SET);
883
884 UINT16_TO_STREAM(pp, handle);
885 UINT16_TO_STREAM(pp, settings);
886
887 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
888 }
889
btsnd_hcic_write_def_policy_set(uint16_t settings)890 void btsnd_hcic_write_def_policy_set(uint16_t settings) {
891 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
892 uint8_t* pp = (uint8_t*)(p + 1);
893
894 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET;
895 p->offset = 0;
896 UINT16_TO_STREAM(pp, HCI_WRITE_DEF_POLICY_SETTINGS);
897 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET);
898
899 UINT16_TO_STREAM(pp, settings);
900
901 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
902 }
903
btsnd_hcic_set_event_filter(uint8_t filt_type,uint8_t filt_cond_type,uint8_t * filt_cond,uint8_t filt_cond_len)904 void btsnd_hcic_set_event_filter(uint8_t filt_type, uint8_t filt_cond_type,
905 uint8_t* filt_cond, uint8_t filt_cond_len) {
906 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
907 uint8_t* pp = (uint8_t*)(p + 1);
908
909 p->offset = 0;
910
911 UINT16_TO_STREAM(pp, HCI_SET_EVENT_FILTER);
912
913 if (filt_type) {
914 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 2 + filt_cond_len);
915 UINT8_TO_STREAM(pp, (uint8_t)(2 + filt_cond_len));
916
917 UINT8_TO_STREAM(pp, filt_type);
918 UINT8_TO_STREAM(pp, filt_cond_type);
919
920 if (filt_cond_type == HCI_FILTER_COND_DEVICE_CLASS) {
921 DEVCLASS_TO_STREAM(pp, filt_cond);
922 filt_cond += kDevClassLength;
923 DEVCLASS_TO_STREAM(pp, filt_cond);
924 filt_cond += kDevClassLength;
925
926 filt_cond_len -= (2 * kDevClassLength);
927 } else if (filt_cond_type == HCI_FILTER_COND_BD_ADDR) {
928 BDADDR_TO_STREAM(pp, *((RawAddress*)filt_cond));
929 filt_cond += BD_ADDR_LEN;
930
931 filt_cond_len -= BD_ADDR_LEN;
932 }
933
934 if (filt_cond_len) ARRAY_TO_STREAM(pp, filt_cond, filt_cond_len);
935 } else {
936 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 1);
937 UINT8_TO_STREAM(pp, 1);
938
939 UINT8_TO_STREAM(pp, filt_type);
940 }
941
942 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
943 }
944
btsnd_hcic_write_pin_type(uint8_t type)945 void btsnd_hcic_write_pin_type(uint8_t type) {
946 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
947 uint8_t* pp = (uint8_t*)(p + 1);
948
949 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
950 p->offset = 0;
951
952 UINT16_TO_STREAM(pp, HCI_WRITE_PIN_TYPE);
953 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
954
955 UINT8_TO_STREAM(pp, type);
956
957 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
958 }
959
btsnd_hcic_delete_stored_key(const RawAddress & bd_addr,bool delete_all_flag)960 void btsnd_hcic_delete_stored_key(const RawAddress& bd_addr,
961 bool delete_all_flag) {
962 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
963 uint8_t* pp = (uint8_t*)(p + 1);
964
965 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DELETE_STORED_KEY;
966 p->offset = 0;
967
968 UINT16_TO_STREAM(pp, HCI_DELETE_STORED_LINK_KEY);
969 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DELETE_STORED_KEY);
970
971 BDADDR_TO_STREAM(pp, bd_addr);
972 UINT8_TO_STREAM(pp, delete_all_flag);
973
974 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
975 }
976
btsnd_hcic_change_name(BD_NAME name)977 void btsnd_hcic_change_name(BD_NAME name) {
978 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
979 uint8_t* pp = (uint8_t*)(p + 1);
980 uint16_t len = strlen((char*)name) + 1;
981
982 memset(pp, 0, HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME);
983
984 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME;
985 p->offset = 0;
986
987 UINT16_TO_STREAM(pp, HCI_CHANGE_LOCAL_NAME);
988 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_NAME);
989
990 if (len > HCIC_PARAM_SIZE_CHANGE_NAME) len = HCIC_PARAM_SIZE_CHANGE_NAME;
991
992 ARRAY_TO_STREAM(pp, name, len);
993
994 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
995 }
996
btsnd_hcic_read_name(void)997 void btsnd_hcic_read_name(void) {
998 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
999 uint8_t* pp = (uint8_t*)(p + 1);
1000
1001 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD;
1002 p->offset = 0;
1003
1004 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_NAME);
1005 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD);
1006
1007 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1008 }
1009
btsnd_hcic_write_page_tout(uint16_t timeout)1010 void btsnd_hcic_write_page_tout(uint16_t timeout) {
1011 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1012 uint8_t* pp = (uint8_t*)(p + 1);
1013
1014 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2;
1015 p->offset = 0;
1016
1017 UINT16_TO_STREAM(pp, HCI_WRITE_PAGE_TOUT);
1018 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2);
1019
1020 UINT16_TO_STREAM(pp, timeout);
1021
1022 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1023 }
1024
btsnd_hcic_write_scan_enable(uint8_t flag)1025 void btsnd_hcic_write_scan_enable(uint8_t flag) {
1026 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1027 uint8_t* pp = (uint8_t*)(p + 1);
1028
1029 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1030 p->offset = 0;
1031
1032 UINT16_TO_STREAM(pp, HCI_WRITE_SCAN_ENABLE);
1033 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1034
1035 UINT8_TO_STREAM(pp, flag);
1036
1037 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1038 }
1039
btsnd_hcic_write_pagescan_cfg(uint16_t interval,uint16_t window)1040 void btsnd_hcic_write_pagescan_cfg(uint16_t interval, uint16_t window) {
1041 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1042 uint8_t* pp = (uint8_t*)(p + 1);
1043
1044 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG;
1045 p->offset = 0;
1046
1047 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_CFG);
1048 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG);
1049
1050 UINT16_TO_STREAM(pp, interval);
1051 UINT16_TO_STREAM(pp, window);
1052
1053 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1054 }
1055
btsnd_hcic_write_inqscan_cfg(uint16_t interval,uint16_t window)1056 void btsnd_hcic_write_inqscan_cfg(uint16_t interval, uint16_t window) {
1057 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1058 uint8_t* pp = (uint8_t*)(p + 1);
1059
1060 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG;
1061 p->offset = 0;
1062
1063 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRYSCAN_CFG);
1064 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG);
1065
1066 UINT16_TO_STREAM(pp, interval);
1067 UINT16_TO_STREAM(pp, window);
1068
1069 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1070 }
1071
btsnd_hcic_write_auth_enable(uint8_t flag)1072 void btsnd_hcic_write_auth_enable(uint8_t flag) {
1073 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1074 uint8_t* pp = (uint8_t*)(p + 1);
1075
1076 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1077 p->offset = 0;
1078
1079 UINT16_TO_STREAM(pp, HCI_WRITE_AUTHENTICATION_ENABLE);
1080 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1081
1082 UINT8_TO_STREAM(pp, flag);
1083
1084 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1085 }
1086
btsnd_hcic_write_dev_class(DEV_CLASS dev_class)1087 void btsnd_hcic_write_dev_class(DEV_CLASS dev_class) {
1088 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1089 uint8_t* pp = (uint8_t*)(p + 1);
1090
1091 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM3;
1092 p->offset = 0;
1093
1094 UINT16_TO_STREAM(pp, HCI_WRITE_CLASS_OF_DEVICE);
1095 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM3);
1096
1097 DEVCLASS_TO_STREAM(pp, dev_class);
1098
1099 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1100 }
1101
btsnd_hcic_write_voice_settings(uint16_t flags)1102 void btsnd_hcic_write_voice_settings(uint16_t flags) {
1103 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1104 uint8_t* pp = (uint8_t*)(p + 1);
1105
1106 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2;
1107 p->offset = 0;
1108
1109 UINT16_TO_STREAM(pp, HCI_WRITE_VOICE_SETTINGS);
1110 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2);
1111
1112 UINT16_TO_STREAM(pp, flags);
1113
1114 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1115 }
1116
btsnd_hcic_write_auto_flush_tout(uint16_t handle,uint16_t tout)1117 void btsnd_hcic_write_auto_flush_tout(uint16_t handle, uint16_t tout) {
1118 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1119 uint8_t* pp = (uint8_t*)(p + 1);
1120
1121 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT;
1122 p->offset = 0;
1123
1124 UINT16_TO_STREAM(pp, HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT);
1125 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT);
1126
1127 UINT16_TO_STREAM(pp, handle);
1128 UINT16_TO_STREAM(pp, tout);
1129
1130 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1131 }
1132
btsnd_hcic_read_tx_power(uint16_t handle,uint8_t type)1133 void btsnd_hcic_read_tx_power(uint16_t handle, uint8_t type) {
1134 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1135 uint8_t* pp = (uint8_t*)(p + 1);
1136
1137 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_TX_POWER;
1138 p->offset = 0;
1139
1140 UINT16_TO_STREAM(pp, HCI_READ_TRANSMIT_POWER_LEVEL);
1141 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_TX_POWER);
1142
1143 UINT16_TO_STREAM(pp, handle);
1144 UINT8_TO_STREAM(pp, type);
1145
1146 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1147 }
1148
btsnd_hcic_write_link_super_tout(uint16_t handle,uint16_t timeout)1149 void btsnd_hcic_write_link_super_tout(uint16_t handle, uint16_t timeout) {
1150 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1151 uint8_t* pp = (uint8_t*)(p + 1);
1152
1153 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT;
1154 p->offset = 0;
1155
1156 UINT16_TO_STREAM(pp, HCI_WRITE_LINK_SUPER_TOUT);
1157 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT);
1158
1159 UINT16_TO_STREAM(pp, handle);
1160 UINT16_TO_STREAM(pp, timeout);
1161
1162 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1163 }
1164
btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac,LAP * const iac_lap)1165 void btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac, LAP* const iac_lap) {
1166 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1167 uint8_t* pp = (uint8_t*)(p + 1);
1168
1169 p->len = HCIC_PREAMBLE_SIZE + 1 + (LAP_LEN * num_cur_iac);
1170 p->offset = 0;
1171
1172 UINT16_TO_STREAM(pp, HCI_WRITE_CURRENT_IAC_LAP);
1173 UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE);
1174
1175 UINT8_TO_STREAM(pp, num_cur_iac);
1176
1177 for (int i = 0; i < num_cur_iac; i++) LAP_TO_STREAM(pp, iac_lap[i]);
1178
1179 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1180 }
1181
1182 /******************************************
1183 * Lisbon Features
1184 ******************************************/
btsnd_hcic_sniff_sub_rate(uint16_t handle,uint16_t max_lat,uint16_t min_remote_lat,uint16_t min_local_lat)1185 void btsnd_hcic_sniff_sub_rate(uint16_t handle, uint16_t max_lat,
1186 uint16_t min_remote_lat,
1187 uint16_t min_local_lat) {
1188 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1189 uint8_t* pp = (uint8_t*)(p + 1);
1190
1191 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_SUB_RATE;
1192 p->offset = 0;
1193
1194 UINT16_TO_STREAM(pp, HCI_SNIFF_SUB_RATE);
1195 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_SUB_RATE);
1196
1197 UINT16_TO_STREAM(pp, handle);
1198 UINT16_TO_STREAM(pp, max_lat);
1199 UINT16_TO_STREAM(pp, min_remote_lat);
1200 UINT16_TO_STREAM(pp, min_local_lat);
1201
1202 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1203 }
1204
1205 /**** Extended Inquiry Response Commands ****/
btsnd_hcic_write_ext_inquiry_response(void * buffer,uint8_t fec_req)1206 void btsnd_hcic_write_ext_inquiry_response(void* buffer, uint8_t fec_req) {
1207 BT_HDR* p = (BT_HDR*)buffer;
1208 uint8_t* pp = (uint8_t*)(p + 1);
1209
1210 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXT_INQ_RESP;
1211 p->offset = 0;
1212
1213 UINT16_TO_STREAM(pp, HCI_WRITE_EXT_INQ_RESPONSE);
1214 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXT_INQ_RESP);
1215
1216 UINT8_TO_STREAM(pp, fec_req);
1217
1218 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1219 }
1220
btsnd_hcic_io_cap_req_reply(const RawAddress & bd_addr,uint8_t capability,uint8_t oob_present,uint8_t auth_req)1221 void btsnd_hcic_io_cap_req_reply(const RawAddress& bd_addr, uint8_t capability,
1222 uint8_t oob_present, uint8_t auth_req) {
1223 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1224 uint8_t* pp = (uint8_t*)(p + 1);
1225
1226 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_RESP;
1227 p->offset = 0;
1228
1229 UINT16_TO_STREAM(pp, HCI_IO_CAPABILITY_REQUEST_REPLY);
1230 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_RESP);
1231
1232 BDADDR_TO_STREAM(pp, bd_addr);
1233 UINT8_TO_STREAM(pp, capability);
1234 UINT8_TO_STREAM(pp, oob_present);
1235 UINT8_TO_STREAM(pp, auth_req);
1236
1237 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1238 }
1239
btsnd_hcic_enhanced_set_up_synchronous_connection(uint16_t conn_handle,enh_esco_params_t * p_params)1240 void btsnd_hcic_enhanced_set_up_synchronous_connection(
1241 uint16_t conn_handle, enh_esco_params_t* p_params) {
1242 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1243 uint8_t* pp = (uint8_t*)(p + 1);
1244
1245 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN;
1246 p->offset = 0;
1247
1248 UINT16_TO_STREAM(pp, HCI_ENH_SETUP_ESCO_CONNECTION);
1249 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN);
1250
1251 UINT16_TO_STREAM(pp, conn_handle);
1252 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth);
1253 UINT32_TO_STREAM(pp, p_params->receive_bandwidth);
1254 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format);
1255 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id);
1256 UINT16_TO_STREAM(pp,
1257 p_params->transmit_coding_format.vendor_specific_codec_id);
1258 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format);
1259 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id);
1260 UINT16_TO_STREAM(pp,
1261 p_params->receive_coding_format.vendor_specific_codec_id);
1262 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size);
1263 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size);
1264 UINT32_TO_STREAM(pp, p_params->input_bandwidth);
1265 UINT32_TO_STREAM(pp, p_params->output_bandwidth);
1266 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format);
1267 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id);
1268 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id);
1269 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format);
1270 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id);
1271 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id);
1272 UINT16_TO_STREAM(pp, p_params->input_coded_data_size);
1273 UINT16_TO_STREAM(pp, p_params->output_coded_data_size);
1274 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format);
1275 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format);
1276 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position);
1277 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position);
1278 UINT8_TO_STREAM(pp, p_params->input_data_path);
1279 UINT8_TO_STREAM(pp, p_params->output_data_path);
1280 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size);
1281 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size);
1282 UINT16_TO_STREAM(pp, p_params->max_latency_ms);
1283 UINT16_TO_STREAM(pp, p_params->packet_types);
1284 UINT8_TO_STREAM(pp, p_params->retransmission_effort);
1285
1286 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1287 }
1288
btsnd_hcic_enhanced_accept_synchronous_connection(const RawAddress & bd_addr,enh_esco_params_t * p_params)1289 void btsnd_hcic_enhanced_accept_synchronous_connection(
1290 const RawAddress& bd_addr, enh_esco_params_t* p_params) {
1291 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1292 uint8_t* pp = (uint8_t*)(p + 1);
1293
1294 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN;
1295 p->offset = 0;
1296
1297 UINT16_TO_STREAM(pp, HCI_ENH_ACCEPT_ESCO_CONNECTION);
1298 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN);
1299
1300 BDADDR_TO_STREAM(pp, bd_addr);
1301 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth);
1302 UINT32_TO_STREAM(pp, p_params->receive_bandwidth);
1303 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format);
1304 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id);
1305 UINT16_TO_STREAM(pp,
1306 p_params->transmit_coding_format.vendor_specific_codec_id);
1307 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format);
1308 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id);
1309 UINT16_TO_STREAM(pp,
1310 p_params->receive_coding_format.vendor_specific_codec_id);
1311 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size);
1312 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size);
1313 UINT32_TO_STREAM(pp, p_params->input_bandwidth);
1314 UINT32_TO_STREAM(pp, p_params->output_bandwidth);
1315 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format);
1316 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id);
1317 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id);
1318 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format);
1319 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id);
1320 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id);
1321 UINT16_TO_STREAM(pp, p_params->input_coded_data_size);
1322 UINT16_TO_STREAM(pp, p_params->output_coded_data_size);
1323 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format);
1324 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format);
1325 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position);
1326 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position);
1327 UINT8_TO_STREAM(pp, p_params->input_data_path);
1328 UINT8_TO_STREAM(pp, p_params->output_data_path);
1329 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size);
1330 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size);
1331 UINT16_TO_STREAM(pp, p_params->max_latency_ms);
1332 UINT16_TO_STREAM(pp, p_params->packet_types);
1333 UINT8_TO_STREAM(pp, p_params->retransmission_effort);
1334
1335 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1336 }
1337
btsnd_hcic_io_cap_req_neg_reply(const RawAddress & bd_addr,uint8_t err_code)1338 void btsnd_hcic_io_cap_req_neg_reply(const RawAddress& bd_addr,
1339 uint8_t err_code) {
1340 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1341 uint8_t* pp = (uint8_t*)(p + 1);
1342
1343 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY;
1344 p->offset = 0;
1345
1346 UINT16_TO_STREAM(pp, HCI_IO_CAP_REQ_NEG_REPLY);
1347 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY);
1348
1349 BDADDR_TO_STREAM(pp, bd_addr);
1350 UINT8_TO_STREAM(pp, err_code);
1351
1352 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1353 }
1354
btsnd_hcic_read_local_oob_data(void)1355 void btsnd_hcic_read_local_oob_data(void) {
1356 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1357 uint8_t* pp = (uint8_t*)(p + 1);
1358
1359 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB;
1360 p->offset = 0;
1361
1362 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_DATA);
1363 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB);
1364
1365 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1366 }
1367
btsnd_hcic_read_local_oob_extended_data(void)1368 void btsnd_hcic_read_local_oob_extended_data(void) {
1369 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1370 uint8_t* pp = (uint8_t*)(p + 1);
1371
1372 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED;
1373 p->offset = 0;
1374
1375 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_EXTENDED_DATA);
1376 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED);
1377
1378 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1379 }
1380
btsnd_hcic_user_conf_reply(const RawAddress & bd_addr,bool is_yes)1381 void btsnd_hcic_user_conf_reply(const RawAddress& bd_addr, bool is_yes) {
1382 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1383 uint8_t* pp = (uint8_t*)(p + 1);
1384
1385 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_UCONF_REPLY;
1386 p->offset = 0;
1387
1388 if (!is_yes) {
1389 /* Negative reply */
1390 UINT16_TO_STREAM(pp, HCI_USER_CONF_VALUE_NEG_REPLY);
1391 } else {
1392 /* Confirmation */
1393 UINT16_TO_STREAM(pp, HCI_USER_CONF_REQUEST_REPLY);
1394 }
1395
1396 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_UCONF_REPLY);
1397
1398 BDADDR_TO_STREAM(pp, bd_addr);
1399
1400 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1401 }
1402
btsnd_hcic_user_passkey_reply(const RawAddress & bd_addr,uint32_t value)1403 void btsnd_hcic_user_passkey_reply(const RawAddress& bd_addr, uint32_t value) {
1404 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1405 uint8_t* pp = (uint8_t*)(p + 1);
1406
1407 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_REPLY;
1408 p->offset = 0;
1409
1410 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_REPLY);
1411 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_REPLY);
1412
1413 BDADDR_TO_STREAM(pp, bd_addr);
1414 UINT32_TO_STREAM(pp, value);
1415
1416 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1417 }
1418
btsnd_hcic_user_passkey_neg_reply(const RawAddress & bd_addr)1419 void btsnd_hcic_user_passkey_neg_reply(const RawAddress& bd_addr) {
1420 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1421 uint8_t* pp = (uint8_t*)(p + 1);
1422
1423 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY;
1424 p->offset = 0;
1425
1426 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_NEG_REPLY);
1427 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY);
1428
1429 BDADDR_TO_STREAM(pp, bd_addr);
1430
1431 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1432 }
1433
btsnd_hcic_rem_oob_reply(const RawAddress & bd_addr,const Octet16 & c,const Octet16 & r)1434 void btsnd_hcic_rem_oob_reply(const RawAddress& bd_addr, const Octet16& c,
1435 const Octet16& r) {
1436 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1437 uint8_t* pp = (uint8_t*)(p + 1);
1438
1439 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_REPLY;
1440 p->offset = 0;
1441
1442 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_REPLY);
1443 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_REPLY);
1444
1445 BDADDR_TO_STREAM(pp, bd_addr);
1446 ARRAY16_TO_STREAM(pp, c.data());
1447 ARRAY16_TO_STREAM(pp, r.data());
1448
1449 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1450 }
1451
btsnd_hcic_rem_oob_neg_reply(const RawAddress & bd_addr)1452 void btsnd_hcic_rem_oob_neg_reply(const RawAddress& bd_addr) {
1453 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1454 uint8_t* pp = (uint8_t*)(p + 1);
1455
1456 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY;
1457 p->offset = 0;
1458
1459 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_NEG_REPLY);
1460 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY);
1461
1462 BDADDR_TO_STREAM(pp, bd_addr);
1463
1464 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1465 }
1466
1467 /**** end of Simple Pairing Commands ****/
1468
1469 /*************************
1470 * End of Lisbon Commands
1471 *************************/
1472
btsnd_hcic_read_rssi(uint16_t handle)1473 void btsnd_hcic_read_rssi(uint16_t handle) {
1474 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1475 uint8_t* pp = (uint8_t*)(p + 1);
1476
1477 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1478 p->offset = 0;
1479
1480 UINT16_TO_STREAM(pp, HCI_READ_RSSI);
1481 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1482
1483 UINT16_TO_STREAM(pp, handle);
1484
1485 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1486 }
1487
read_encryption_key_size_complete(ReadEncKeySizeCb cb,uint8_t * return_parameters,uint16_t)1488 static void read_encryption_key_size_complete(
1489 ReadEncKeySizeCb cb, uint8_t* return_parameters,
1490 uint16_t /* return_parameters_length */) {
1491 uint8_t status;
1492 uint16_t handle;
1493 uint8_t key_size;
1494 STREAM_TO_UINT8(status, return_parameters);
1495 STREAM_TO_UINT16(handle, return_parameters);
1496 STREAM_TO_UINT8(key_size, return_parameters);
1497
1498 std::move(cb).Run(status, handle, key_size);
1499 }
1500
btsnd_hcic_read_encryption_key_size(uint16_t handle,ReadEncKeySizeCb cb)1501 void btsnd_hcic_read_encryption_key_size(uint16_t handle, ReadEncKeySizeCb cb) {
1502 constexpr uint8_t len = 2;
1503 uint8_t param[len];
1504 memset(param, 0, len);
1505
1506 uint8_t* p = param;
1507 UINT16_TO_STREAM(p, handle);
1508
1509 btu_hcif_send_cmd_with_cb(FROM_HERE, HCI_READ_ENCR_KEY_SIZE, param, len,
1510 base::Bind(&read_encryption_key_size_complete, base::Passed(&cb)));
1511 }
1512
btsnd_hcic_read_failed_contact_counter(uint16_t handle)1513 void btsnd_hcic_read_failed_contact_counter(uint16_t handle) {
1514 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1515 uint8_t* pp = (uint8_t*)(p + 1);
1516
1517 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1518 p->offset = 0;
1519
1520 UINT16_TO_STREAM(pp, HCI_READ_FAILED_CONTACT_COUNTER);
1521 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1522
1523 UINT16_TO_STREAM(pp, handle);
1524
1525 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1526 }
1527
btsnd_hcic_enable_test_mode(void)1528 void btsnd_hcic_enable_test_mode(void) {
1529 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1530 uint8_t* pp = (uint8_t*)(p + 1);
1531
1532 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD;
1533 p->offset = 0;
1534
1535 UINT16_TO_STREAM(pp, HCI_ENABLE_DEV_UNDER_TEST_MODE);
1536 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD);
1537
1538 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1539 }
1540
btsnd_hcic_write_inqscan_type(uint8_t type)1541 void btsnd_hcic_write_inqscan_type(uint8_t type) {
1542 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1543 uint8_t* pp = (uint8_t*)(p + 1);
1544
1545 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1546 p->offset = 0;
1547
1548 UINT16_TO_STREAM(pp, HCI_WRITE_INQSCAN_TYPE);
1549 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1550
1551 UINT8_TO_STREAM(pp, type);
1552
1553 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1554 }
1555
btsnd_hcic_write_inquiry_mode(uint8_t mode)1556 void btsnd_hcic_write_inquiry_mode(uint8_t mode) {
1557 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1558 uint8_t* pp = (uint8_t*)(p + 1);
1559
1560 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1561 p->offset = 0;
1562
1563 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRY_MODE);
1564 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1565
1566 UINT8_TO_STREAM(pp, mode);
1567
1568 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1569 }
1570
btsnd_hcic_write_pagescan_type(uint8_t type)1571 void btsnd_hcic_write_pagescan_type(uint8_t type) {
1572 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1573 uint8_t* pp = (uint8_t*)(p + 1);
1574
1575 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1576 p->offset = 0;
1577
1578 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_TYPE);
1579 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1580
1581 UINT8_TO_STREAM(pp, type);
1582
1583 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1584 }
1585
btsnd_hcic_vendor_spec_complete(tBTM_VSC_CMPL_CB * p_vsc_cplt_cback,uint16_t opcode,uint8_t * data,uint16_t len)1586 static void btsnd_hcic_vendor_spec_complete(tBTM_VSC_CMPL_CB* p_vsc_cplt_cback,
1587 uint16_t opcode, uint8_t* data,
1588 uint16_t len) {
1589 /* If there was a callback address for vcs complete, call it */
1590 if (p_vsc_cplt_cback) {
1591 tBTM_VSC_CMPL vcs_cplt_params;
1592 vcs_cplt_params.opcode = opcode;
1593 vcs_cplt_params.param_len = len;
1594 vcs_cplt_params.p_param_buf = data;
1595 /* Call the VSC complete callback function */
1596 (*p_vsc_cplt_cback)(&vcs_cplt_params);
1597 }
1598 }
1599
btsnd_hcic_vendor_spec_cmd(uint16_t opcode,uint8_t len,uint8_t * p_data,tBTM_VSC_CMPL_CB * p_cmd_cplt_cback)1600 void btsnd_hcic_vendor_spec_cmd(uint16_t opcode, uint8_t len, uint8_t* p_data,
1601 tBTM_VSC_CMPL_CB* p_cmd_cplt_cback) {
1602 uint16_t v_opcode = HCI_GRP_VENDOR_SPECIFIC | opcode;
1603
1604 btu_hcif_send_cmd_with_cb(
1605 FROM_HERE, v_opcode, p_data, len,
1606 base::BindOnce(&btsnd_hcic_vendor_spec_complete,
1607 base::Unretained(p_cmd_cplt_cback), v_opcode));
1608 }
1609
btsnd_hcic_configure_data_path(hci_data_direction_t data_path_direction,uint8_t data_path_id,std::vector<uint8_t> vendor_config)1610 void btsnd_hcic_configure_data_path(hci_data_direction_t data_path_direction,
1611 uint8_t data_path_id,
1612 std::vector<uint8_t> vendor_config) {
1613 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1614 uint8_t* pp = (uint8_t*)(p + 1);
1615 uint8_t size = static_cast<uint8_t>(vendor_config.size());
1616 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size;
1617 p->offset = 0;
1618
1619 UINT16_TO_STREAM(pp, HCI_CONFIGURE_DATA_PATH);
1620 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size);
1621 UINT8_TO_STREAM(pp, data_path_direction);
1622 UINT8_TO_STREAM(pp, data_path_id);
1623 UINT8_TO_STREAM(pp, vendor_config.size());
1624 if (size != 0) {
1625 ARRAY_TO_STREAM(pp, vendor_config.data(), size);
1626 }
1627
1628 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1629 }
1630
1631 namespace bluetooth::legacy::hci {
1632 class InterfaceImpl : public Interface {
Disconnect(uint16_t handle,uint8_t reason) const1633 void Disconnect(uint16_t handle, uint8_t reason) const override {
1634 btsnd_hcic_disconnect(handle, reason);
1635 }
ChangeConnectionPacketType(uint16_t handle,uint16_t packet_types) const1636 void ChangeConnectionPacketType(uint16_t handle,
1637 uint16_t packet_types) const override {
1638 btsnd_hcic_change_conn_type(handle, packet_types);
1639 }
StartRoleSwitch(const RawAddress & bd_addr,uint8_t role) const1640 void StartRoleSwitch(const RawAddress& bd_addr, uint8_t role) const override {
1641 btsnd_hcic_switch_role(bd_addr, role);
1642 }
ConfigureDataPath(hci_data_direction_t data_path_direction,uint8_t data_path_id,std::vector<uint8_t> vendor_config) const1643 void ConfigureDataPath(hci_data_direction_t data_path_direction,
1644 uint8_t data_path_id,
1645 std::vector<uint8_t> vendor_config) const override {
1646 btsnd_hcic_configure_data_path(data_path_direction, data_path_id,
1647 vendor_config);
1648 }
1649 };
1650
1651 namespace {
1652 const InterfaceImpl interface_;
1653 }
1654
GetInterface()1655 const Interface& GetInterface() { return interface_; }
1656 } // namespace bluetooth::legacy::hci
1657