Home
last modified time | relevance | path

Searched refs:bb2 (Results 1 – 10 of 10) sorted by relevance

/frameworks/libs/binary_translation/backend/x86_64/
Dmachine_ir_analysis_test.cc56 auto bb2 = machine_ir.NewBasicBlock(); in TEST() local
58 machine_ir.AddEdge(bb1, bb2); in TEST()
59 machine_ir.AddEdge(bb2, bb2); in TEST()
60 machine_ir.AddEdge(bb2, bb3); in TEST()
63 builder.Gen<PseudoBranch>(bb2); in TEST()
65 builder.StartBasicBlock(bb2); in TEST()
66 builder.Gen<PseudoCondBranch>(CodeEmitter::Condition::kZero, bb2, bb3, x86_64::kMachineRegFLAGS); in TEST()
75 CheckLoopContent(loop, {bb2}); in TEST()
88 auto bb2 = machine_ir.NewBasicBlock(); in TEST() local
91 machine_ir.AddEdge(bb1, bb2); in TEST()
[all …]
Dmachine_ir_test_corpus.cc40 auto* bb2 = machine_ir->NewBasicBlock(); in BuildDataFlowAcrossBasicBlocks() local
43 machine_ir->AddEdge(bb1, bb2); in BuildDataFlowAcrossBasicBlocks()
44 machine_ir->AddEdge(bb2, bb3); in BuildDataFlowAcrossBasicBlocks()
49 builder.Gen<PseudoBranch>(bb2); in BuildDataFlowAcrossBasicBlocks()
51 builder.StartBasicBlock(bb2); in BuildDataFlowAcrossBasicBlocks()
59 return {bb1, bb2, bb3, vreg1, vreg2}; in BuildDataFlowAcrossBasicBlocks()
72 auto* bb2 = machine_ir->NewBasicBlock(); in BuildDataFlowFromTwoPreds() local
76 machine_ir->AddEdge(bb2, bb3); in BuildDataFlowFromTwoPreds()
82 builder.StartBasicBlock(bb2); in BuildDataFlowFromTwoPreds()
90 return {bb1, bb2, bb3, vreg}; in BuildDataFlowFromTwoPreds()
[all …]
Dmachine_ir_check_test.cc37 auto* bb2 = machine_ir.NewBasicBlock(); in TEST() local
39 machine_ir.bb_list().push_back(bb2); in TEST()
41 auto* bad_edge = NewInArena<MachineEdge>(&arena, &arena, bb1, bb2); in TEST()
42 auto* good_edge = NewInArena<MachineEdge>(&arena, &arena, bb2, bb1); in TEST()
44 bb2->out_edges().push_back(good_edge); in TEST()
54 auto* bb2 = machine_ir.NewBasicBlock(); in TEST() local
56 machine_ir.bb_list().push_back(bb2); in TEST()
58 auto* bad_edge = NewInArena<MachineEdge>(&arena, &arena, bb2, bb1); in TEST()
59 auto* good_edge = NewInArena<MachineEdge>(&arena, &arena, bb1, bb2); in TEST()
61 bb2->in_edges().push_back(good_edge); in TEST()
[all …]
Dmachine_ir_opt_test.cc270 auto bb2 = machine_ir.NewBasicBlock(); in TEST() local
274 machine_ir.AddEdge(bb2, bb3); in TEST()
275 machine_ir.AddEdge(bb2, bb4); in TEST()
280 builder.StartBasicBlock(bb2); in TEST()
297 ASSERT_EQ(bb2->out_edges().size(), 2UL); in TEST()
298 int bb4_index_in_bb2 = GetOutEdgeIndex(bb2, bb4); in TEST()
300 EXPECT_EQ(new_bb, bb2->out_edges()[1 - bb4_index_in_bb2]->dst()); in TEST()
315 auto bb2 = machine_ir.NewBasicBlock(); in TEST() local
317 machine_ir.AddEdge(bb1, bb2); in TEST()
318 machine_ir.AddEdge(bb2, bb2); in TEST()
[all …]
Dcontext_liveness_analyzer_test.cc76 auto* bb2 = machine_ir.NewBasicBlock(); in TEST() local
77 machine_ir.AddEdge(bb1, bb2); in TEST()
83 builder.Gen<PseudoBranch>(bb2); in TEST()
85 builder.StartBasicBlock(bb2); in TEST()
94 CheckBBLiveIn(&analyzer, bb2, {0}); in TEST()
103 auto* bb2 = machine_ir.NewBasicBlock(); in TEST() local
104 machine_ir.AddEdge(bb1, bb2); in TEST()
110 builder.Gen<PseudoBranch>(bb2); in TEST()
112 builder.StartBasicBlock(bb2); in TEST()
123 CheckBBLiveIn(&analyzer, bb2, {0, 1, 2}); in TEST()
[all …]
Drename_vregs_test.cc66 auto* bb2 = machine_ir.NewBasicBlock(); in TEST() local
68 machine_ir.AddEdge(bb1, bb2); in TEST()
72 builder.Gen<PseudoBranch>(bb2); in TEST()
74 builder.StartBasicBlock(bb2); in TEST()
86 ASSERT_EQ(bb2->insn_list().size(), 2U); in TEST()
87 it = bb2->insn_list().begin(); in TEST()
99 auto [bb1, bb2, bb3, vreg1, vreg2] = BuildDataFlowAcrossBasicBlocks(&machine_ir); in TEST()
120 ASSERT_EQ(bb2->insn_list().size(), 4U); in TEST()
122 it = bb2->insn_list().begin(); in TEST()
162 auto [bb1, bb2, bb3, vreg] = BuildDataFlowFromTwoPreds(&machine_ir); in TEST()
[all …]
Dmachine_ir_test.cc62 auto* bb2 = machine_ir.NewBasicBlock(); in TEST() local
65 machine_ir.AddEdge(bb1, bb2); in TEST()
71 builder.Gen<PseudoCondBranch>(CodeEmitter::Condition::kZero, bb2, bb3, x86_64::kMachineRegFLAGS); in TEST()
73 builder.StartBasicBlock(bb2); in TEST()
94 EXPECT_EQ(new_bb->out_edges().front()->dst(), bb2); in TEST()
98 EXPECT_EQ(bb2->in_edges().size(), 1UL); in TEST()
99 EXPECT_EQ(bb2->in_edges().front()->src(), new_bb); in TEST()
100 EXPECT_EQ(bb2->in_edges().front()->dst(), bb2); in TEST()
Drename_vregs_local_test.cc262 auto* bb2 = machine_ir.NewBasicBlock(); in TEST() local
273 builder.Gen<PseudoBranch>(bb2); in TEST()
275 builder.StartBasicBlock(bb2); in TEST()
281 bb2->live_in().push_back(vreg1); in TEST()
282 bb2->live_in().push_back(vreg2); in TEST()
284 machine_ir.AddEdge(bb1, bb2); in TEST()
289 EXPECT_EQ(bb2->insn_list().size(), 2UL); in TEST()
297 auto insn_it = bb2->insn_list().begin(); in TEST()
299 EXPECT_EQ(new_vreg1, bb2->live_in()[0]); in TEST()
300 EXPECT_EQ(new_vreg2, bb2->live_in()[1]); in TEST()
Dliveness_analyzer_test.cc184 auto [bb1, bb2, bb3, vreg1, vreg2] = BuildDataFlowAcrossBasicBlocks(&machine_ir); in TEST()
190 ExpectTwoLiveIns(&liveness, bb2, vreg1, vreg2); in TEST()
198 auto [bb1, bb2, bb3, vreg] = BuildDataFlowFromTwoPreds(&machine_ir); in TEST()
204 ExpectNoLiveIns(&liveness, bb2, vreg); in TEST()
212 auto [bb1, bb2, bb3, vreg] = BuildDataFlowToTwoSuccs(&machine_ir); in TEST()
218 ExpectSingleLiveIn(&liveness, bb2, vreg); in TEST()
226 auto [bb1, bb2, bb3, bb4, vreg] = BuildDataFlowAcrossEmptyLoop(&machine_ir); in TEST()
232 ExpectSingleLiveIn(&liveness, bb2, vreg); in TEST()
/frameworks/libs/binary_translation/heavy_optimizer/riscv64/
Dfrontend_tests.cc274 auto* bb2 = bb1->out_edges()[1]->dst(); in TEST() local
275 CheckBasicBlockEndsWith(bb2, kMachineOpPseudoCondBranch); in TEST()
276 ASSERT_EQ(bb2->out_edges()[1]->dst(), bb1); in TEST()
283 ASSERT_EQ(bb4->out_edges()[1]->dst(), bb2); in TEST()
340 auto* bb2 = bb4->out_edges()[0]->dst(); in TEST() local
341 CheckBasicBlockEndsWith(bb2, kMachineOpPseudoJump); in TEST()
342 EXPECT_EQ(bb2->out_edges().size(), 0u); in TEST()