171   NewLIR4(is_wide ? WIDE(opcode) : opcode, rs_dest.GetReg(), left_op.GetReg(), right_op.GetReg(),  in GenSelect()
207     int opcode = is_wide ? WIDE(kA64Csel4rrrc) : kA64Csel4rrrc;  in GenSelect()
266       ArmOpcode wide = reg.Is64Bit() ? WIDE(0) : UNWIDE(0);  in OpCmpImmBranch()
272       ArmOpcode wide = reg.Is64Bit() ? WIDE(0) : UNWIDE(0);  in OpCmpImmBranch()
321         opcode = WIDE(opcode);  in OpRegCopyNoInsert()
480     NewLIR3(WIDE(kA64Orr3Rrl), r_magic.GetReg(), rxzr, magic_table[lit].magic64_base);  in SmallLiteralDivRem64()
482       NewLIR3(WIDE(kA64Eor3Rrl), r_magic.GetReg(), r_magic.GetReg(),  in SmallLiteralDivRem64()
485       NewLIR4(WIDE(kA64Add4RRdT), r_magic.GetReg(), r_magic.GetReg(), 1, 0);  in SmallLiteralDivRem64()
631       wide = WIDE(0);  in GenDivRem()
667   NewLIR4((is_long) ? WIDE(kA64Csel4rrrc) : kA64Csel4rrrc, rl_result.reg.GetReg(),  in GenInlinedMinMax()
755     wide = WIDE(0);  in GenInlinedCas()
909   return RawLIR(current_dalvik_offset_, WIDE(kA64Ldr2rp), reg.GetReg(), 0, 0, 0, 0, target);  in OpPcRelLoad()
946   ArmOpcode opcode = reg.Is64Bit() ? WIDE(kA64Subs3rRd) : UNWIDE(kA64Subs3rRd);  in OpDecAndBranch()
999   NewLIR4(WIDE(kA64Sbfm4rrdd), rl_result.reg.GetReg(), As64BitReg(rl_src.reg).GetReg(), 0, 31);  in GenIntToLong()
1427       m2l->NewLIR3(WIDE(kA64Str3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);  in SpillCoreRegs()
1429       m2l->NewLIR4(WIDE(kA64Stp4rrXD), RegStorage::Solo64(reg2).GetReg(),  in SpillCoreRegs()
1446       m2l->NewLIR4(WIDE(kA64Stp4ffXD), RegStorage::FloatSolo64(reg2).GetReg(),  in SpillFPRegs()
1510         m2l->NewLIR4(WIDE(kA64StpPre4ffXD),  in SpillRegsPreIndexed()
1515         m2l->NewLIR4(WIDE(kA64StpPre4ffXD),  in SpillRegsPreIndexed()
1524         m2l->NewLIR4(WIDE(kA64StpPre4ffXD), RegStorage::FloatSolo64(reg2).GetReg(),  in SpillRegsPreIndexed()
1528         m2l->NewLIR4(WIDE(kA64StpPre4ffXD), rs_d0.GetReg(), RegStorage::FloatSolo64(reg1).GetReg(),  in SpillRegsPreIndexed()
1540       m2l->NewLIR4(WIDE(kA64StpPre4rrXD), rs_xzr.GetReg(),  in SpillRegsPreIndexed()
1544       m2l->NewLIR4(WIDE(kA64StpPre4rrXD), RegStorage::Solo64(reg2).GetReg(),  in SpillRegsPreIndexed()
1558         m2l->NewLIR4(WIDE(kA64Stp4ffXD), RegStorage::FloatSolo64(reg2).GetReg(),  in SpillRegsPreIndexed()
1570       m2l->NewLIR3(WIDE(kA64Str3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(),  in SpillRegsPreIndexed()
1580     m2l->NewLIR4(WIDE(kA64Stp4rrXD), RegStorage::Solo64(reg2).GetReg(),  in SpillRegsPreIndexed()
1611       m2l->NewLIR3(WIDE(kA64Ldr3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);  in UnSpillCoreRegs()
1614       m2l->NewLIR4(WIDE(kA64Ldp4rrXD), RegStorage::Solo64(reg2).GetReg(),  in UnSpillCoreRegs()
1630       m2l->NewLIR4(WIDE(kA64Ldp4ffXD), RegStorage::FloatSolo64(reg2).GetReg(),  in UnSpillFPRegs()
1689   ArmOpcode wide = (size == k64) ? WIDE(0) : UNWIDE(0);  in GenInlinedReverseBits()