470       uint64_t base = DecodeLogicalImmediate(/*is_wide*/true, magic_table[lit].magic64_base);  in SmallLiteralDivRem64()  local
473         reconstructed_imm = base ^ eor;  in SmallLiteralDivRem64()
475         reconstructed_imm = base + 1;  in SmallLiteralDivRem64()
1420 static void SpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {  in SpillCoreRegs()  argument
1427       m2l->NewLIR3(WIDE(kA64Str3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);  in SpillCoreRegs()
1430                    RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);  in SpillCoreRegs()
1436 static void SpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {  in SpillFPRegs()  argument
1443       m2l->NewLIR3(FWIDE(kA64Str3fXD), RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(),  in SpillFPRegs()
1447                    RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), offset);  in SpillFPRegs()
1452 static int SpillRegsPreSub(Arm64Mir2Lir* m2l, RegStorage base, uint32_t core_reg_mask,  in SpillRegsPreSub()  argument
1474 static int SpillRegsPreIndexed(Arm64Mir2Lir* m2l, RegStorage base, uint32_t core_reg_mask,  in SpillRegsPreIndexed()  argument
1513                      base.GetReg(), -all_offset);  in SpillRegsPreIndexed()
1518                      base.GetReg(), -all_offset);  in SpillRegsPreIndexed()
1525                      RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), -all_offset);  in SpillRegsPreIndexed()
1529                      base.GetReg(), -all_offset);  in SpillRegsPreIndexed()
1541                    RegStorage::Solo64(reg1).GetReg(), base.GetReg(), -all_offset);  in SpillRegsPreIndexed()
1545                    RegStorage::Solo64(reg1).GetReg(), base.GetReg(), -all_offset);  in SpillRegsPreIndexed()
1554         m2l->NewLIR3(FWIDE(kA64Str3fXD), RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(),  in SpillRegsPreIndexed()
1559                      RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), cur_offset);  in SpillRegsPreIndexed()
1570       m2l->NewLIR3(WIDE(kA64Str3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(),  in SpillRegsPreIndexed()
1581                  RegStorage::Solo64(reg1).GetReg(), base.GetReg(), cur_offset);  in SpillRegsPreIndexed()
1589 int Arm64Mir2Lir::SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask,  in SpillRegs()  argument
1598     return SpillRegsPreSub(this, base, core_reg_mask, fp_reg_mask, frame_size);  in SpillRegs()
1600     return SpillRegsPreIndexed(this, base, core_reg_mask, fp_reg_mask, frame_size);  in SpillRegs()
1604 static void UnSpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {  in UnSpillCoreRegs()  argument
1611       m2l->NewLIR3(WIDE(kA64Ldr3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);  in UnSpillCoreRegs()
1615                    RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);  in UnSpillCoreRegs()
1620 static void UnSpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {  in UnSpillFPRegs()  argument
1627       m2l->NewLIR3(FWIDE(kA64Ldr3fXD), RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(),  in UnSpillFPRegs()
1631                    RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), offset);  in UnSpillFPRegs()
1636 void Arm64Mir2Lir::UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask,  in UnspillRegs()  argument