93   int offset;  in EmitBranch()  local
95     offset = label->Position() - buffer_.Size();  in EmitBranch()
98     offset = label->position_;  in EmitBranch()
102     Beq(rt, rs, (offset >> 2) & kBranchOffsetMask);  in EmitBranch()
104     Bne(rt, rs, (offset >> 2) & kBranchOffsetMask);  in EmitBranch()
109   int offset;  in EmitJump()  local
111     offset = label->Position() - buffer_.Size();  in EmitJump()
114     offset = label->position_;  in EmitJump()
118     Jal((offset >> 2) & kJumpOffsetMask);  in EmitJump()
120     J((offset >> 2) & kJumpOffsetMask);  in EmitJump()
124 int32_t MipsAssembler::EncodeBranchOffset(int offset, int32_t inst, bool is_jump) {  in EncodeBranchOffset()  argument
125   CHECK_ALIGNED(offset, 4);  in EncodeBranchOffset()
126   CHECK(IsInt(POPCOUNT(kBranchOffsetMask), offset)) << offset;  in EncodeBranchOffset()
129   offset >>= 2;  in EncodeBranchOffset()
131     offset &= kJumpOffsetMask;  in EncodeBranchOffset()
132     return (inst & ~kJumpOffsetMask) | offset;  in EncodeBranchOffset()
134     offset &= kBranchOffsetMask;  in EncodeBranchOffset()
135     return (inst & ~kBranchOffsetMask) | offset;  in EncodeBranchOffset()
154     int32_t offset = is_jump ? bound_pc - position : bound_pc - position - 4;  in Bind()  local
155     int32_t encoded = MipsAssembler::EncodeBranchOffset(offset, next, is_jump);  in Bind()
478                                    int32_t offset) {  in LoadFromOffset()  argument
481       Lb(reg, base, offset);  in LoadFromOffset()
484       Lbu(reg, base, offset);  in LoadFromOffset()
487       Lh(reg, base, offset);  in LoadFromOffset()
490       Lhu(reg, base, offset);  in LoadFromOffset()
493       Lw(reg, base, offset);  in LoadFromOffset()
503 void MipsAssembler::LoadSFromOffset(FRegister reg, Register base, int32_t offset) {  in LoadSFromOffset()  argument
504   Lwc1(reg, base, offset);  in LoadSFromOffset()
507 void MipsAssembler::LoadDFromOffset(DRegister reg, Register base, int32_t offset) {  in LoadDFromOffset()  argument
508   Ldc1(reg, base, offset);  in LoadDFromOffset()
512                                   int32_t offset) {  in StoreToOffset()  argument
515       Sb(reg, base, offset);  in StoreToOffset()
518       Sh(reg, base, offset);  in StoreToOffset()
521       Sw(reg, base, offset);  in StoreToOffset()
531 void MipsAssembler::StoreFToOffset(FRegister reg, Register base, int32_t offset) {  in StoreFToOffset()  argument
532   Swc1(reg, base, offset);  in StoreFToOffset()
535 void MipsAssembler::StoreDToOffset(DRegister reg, Register base, int32_t offset) {  in StoreDToOffset()  argument
536   Sdc1(reg, base, offset);  in StoreDToOffset()
905 void MipsAssembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister mscratch) {  in Call()  argument
911                  base.AsCoreRegister(), offset.Int32Value());  in Call()
916 void MipsAssembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) {  in Call()  argument
923                  scratch.AsCoreRegister(), offset.Int32Value());  in Call()
936 void MipsAssembler::GetCurrentThread(FrameOffset offset,  in GetCurrentThread()  argument
938   StoreToOffset(kStoreWord, S1, SP, offset.Int32Value());  in GetCurrentThread()