Lines Matching refs:op
269 uint32_t op = (instruction >> 21) & 0xf; in DumpArm() local
270 opcode = kDataProcessingOperations[op]; in DumpArm()
271 bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN. in DumpArm()
272 bool is_mov = op == 0b1101 || op == 0b1111; in DumpArm()
400 uint64_t AdvSIMDExpand(uint32_t op, uint32_t cmode, uint32_t imm8) { in AdvSIMDExpand() argument
401 CHECK_EQ(op & 1, op); in AdvSIMDExpand()
421 if ((cmode & 1) == 0 && op == 0) { in AdvSIMDExpand()
424 } else if ((cmode & 1) == 0 && op != 0) { in AdvSIMDExpand()
430 } else if ((cmode & 1) != 0 && op == 0) { in AdvSIMDExpand()
473 uint32_t op = (instr >> 23) & 3; in DumpThumb32() local
477 if (op == 1 || op == 2) { in DumpThumb32()
478 if (op == 1) { in DumpThumb32()
895 uint32_t op = (instr >> 7) & 1; in DumpThumb32() local
902 opcode << (op == 0 ? "vmov" : "vabs") << (S != 0 ? ".f64" : ".f32"); in DumpThumb32()
905 opcode << (op != 0 ? "vsqrt" : "vneg") << (S != 0 ? ".f64" : ".f32"); in DumpThumb32()
910 if (op != 0) { in DumpThumb32()
916 if (op != 0) { in DumpThumb32()
925 opcode << "vcvt" << (op == 0 ? "r" : "") << ".s32.f64"; in DumpThumb32()
929 opcode << "vcvt" << (op == 0 ? "r" : "") << ".s32.f32"; in DumpThumb32()
935 opcode << "vcvt" << (op == 0 ? "r" : "") << ".u32.f64"; in DumpThumb32()
939 opcode << "vcvt" << (op == 0 ? "r" : "") << ".u32.f32"; in DumpThumb32()
945 opcode << "vcvt.f64." << (op == 0 ? "u" : "s") << "32"; in DumpThumb32()
949 opcode << "vcvt.f32." << (op == 0 ? "u" : "s") << "32"; in DumpThumb32()
953 if (op == 1) { in DumpThumb32()
979 uint32_t op = op3 & 1; in DumpThumb32() local
983 if (op) { in DumpThumb32()
1838 uint16_t op = (instr >> 11) & 1; in DumpThumb16() local
1842 opcode << (op != 0 ? "cbnz" : "cbz"); in DumpThumb16()
1851 uint16_t op = (instr >> 6) & 3; in DumpThumb16() local
1852 opcode << kThumbReverseOperations[op]; in DumpThumb16()