/external/llvm/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 1327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local 1473 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local 1578 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeSORegMemOperand() local 1623 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode3Instruction() local 1813 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeRFEInstruction() local 1844 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeQADDInstruction() local 1866 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeMemMultipleWritebackInstruction() local 2097 unsigned Rn = fieldFromInstruction(Insn, 0, 4); in DecodeSMLAInstruction() local 2126 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeAddrModeImm12Operand() local 2144 unsigned Rn = fieldFromInstruction(Val, 9, 4); in DecodeAddrMode5Operand() local [all …]
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/external/lldb/source/Plugins/Instruction/ARM/ |
D | EmulateInstructionARM.cpp | 1906 uint32_t Rn; // This function assumes Rn is the SP, but we should verify that. in EmulateSTRRtSP() local 2391 uint32_t Rn; // the base register which contains the address of the table of branch lengths in EmulateTB() local 2530 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); in EmulateADDImmThumb() local 2582 uint32_t Rd, Rn; in EmulateADDImmARM() local 2642 uint32_t Rd, Rn, Rm; in EmulateADDReg() local 2725 uint32_t Rn; // the first operand in EmulateCMNImm() local 2776 uint32_t Rn; // the first operand in EmulateCMNReg() local 2845 uint32_t Rn; // the first operand in EmulateCMPImm() local 2900 uint32_t Rn; // the first operand in EmulateCMPReg() local 3279 uint32_t Rn; // the first operand register in EmulateShiftReg() local [all …]
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/external/llvm/lib/Target/AArch64/Disassembler/ |
D | AArch64Disassembler.cpp | 670 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local 761 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local 856 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local 917 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local 1102 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeExclusiveLdStInstruction() local 1177 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodePairLdStInstruction() local 1306 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeAddSubERegInstruction() local 1363 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeLogicalImmInstruction() local 1469 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeBaseAddSubImm() local
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/external/chromium_org/v8/src/arm/ |
D | disasm-arm.cc | 416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { in FormatNeonMemory() 1573 int Rn = instr->VnValue(); in DecodeSpecialCondition() local 1586 int Rn = instr->VnValue(); in DecodeSpecialCondition() local 1603 int Rn = instr->Bits(19, 16); in DecodeSpecialCondition() local
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D | simulator-arm.cc | 3501 int Rn = instr->VnValue(); in DecodeSpecialCondition() local 3542 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 853 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local 1060 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() local 1096 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode2OpValue() local 1172 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrMode3OpValue() local 1182 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode3OpValue() local 1219 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrModeISOpValue() local
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/external/qemu/disas/ |
D | arm.c | 3454 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local 3535 unsigned int Rn = (given & 0x000f0000) >> 16; in print_insn_thumb32() local
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/external/llvm/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 2742 unsigned Rn = MI->getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local 2766 unsigned Rn = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local 2775 unsigned Rn = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local 2811 unsigned Rn = MI->getOperand(2).getReg(); in getNumMicroOpsSwiftLdSt() local
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/external/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 3291 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local 3337 unsigned Rn = Inst.getOperand(3).getReg(); in validateInstruction() local 3369 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local 3388 unsigned Rn = Inst.getOperand(2).getReg(); in validateInstruction() local
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/external/vixl/src/a64/ |
D | assembler-a64.h | 1407 static Instr Rn(CPURegister rn) { in Rn() function
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/external/chromium_org/v8/src/arm64/ |
D | assembler-arm64.h | 1767 static Instr Rn(CPURegister rn) { in Rn() function
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/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 5690 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); in validateInstruction() local 5749 unsigned Rn = Inst.getOperand(0).getReg(); in validateInstruction() local 7684 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction() local 7708 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction() local
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