1 /* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 18 #define ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 19 20 #include <iosfwd> 21 22 namespace art { 23 namespace arm64 { 24 25 // Values for GP XRegisters - 64bit registers. 26 enum Register { 27 X0 = 0, 28 X1 = 1, 29 X2 = 2, 30 X3 = 3, 31 X4 = 4, 32 X5 = 5, 33 X6 = 6, 34 X7 = 7, 35 X8 = 8, 36 X9 = 9, 37 X10 = 10, 38 X11 = 11, 39 X12 = 12, 40 X13 = 13, 41 X14 = 14, 42 X15 = 15, 43 X16 = 16, 44 X17 = 17, 45 X18 = 18, 46 X19 = 19, 47 X20 = 20, 48 X21 = 21, 49 X22 = 22, 50 X23 = 23, 51 X24 = 24, 52 X25 = 25, 53 X26 = 26, 54 X27 = 27, 55 X28 = 28, 56 X29 = 29, 57 X30 = 30, 58 X31 = 31, 59 TR = 18, // ART Thread Register - Managed Runtime (Caller Saved Reg) 60 ETR = 21, // ART Thread Register - External Calls (Callee Saved Reg) 61 IP0 = 16, // Used as scratch by VIXL. 62 IP1 = 17, // Used as scratch by ART JNI Assembler. 63 FP = 29, 64 LR = 30, 65 SP = 31, // SP is X31 and overlaps with XRZ but we encode it as a 66 // special register, due to the different instruction semantics. 67 XZR = 32, 68 kNumberOfCoreRegisters = 33, 69 kNoRegister = -1, 70 }; 71 std::ostream& operator<<(std::ostream& os, const Register& rhs); 72 73 // Values for GP WRegisters - 32bit registers. 74 enum WRegister { 75 W0 = 0, 76 W1 = 1, 77 W2 = 2, 78 W3 = 3, 79 W4 = 4, 80 W5 = 5, 81 W6 = 6, 82 W7 = 7, 83 W8 = 8, 84 W9 = 9, 85 W10 = 10, 86 W11 = 11, 87 W12 = 12, 88 W13 = 13, 89 W14 = 14, 90 W15 = 15, 91 W16 = 16, 92 W17 = 17, 93 W18 = 18, 94 W19 = 19, 95 W20 = 20, 96 W21 = 21, 97 W22 = 22, 98 W23 = 23, 99 W24 = 24, 100 W25 = 25, 101 W26 = 26, 102 W27 = 27, 103 W28 = 28, 104 W29 = 29, 105 W30 = 30, 106 W31 = 31, 107 WZR = 31, 108 kNumberOfWRegisters = 32, 109 kNoWRegister = -1, 110 }; 111 std::ostream& operator<<(std::ostream& os, const WRegister& rhs); 112 113 // Values for FP DRegisters - double precision floating point. 114 enum DRegister { 115 D0 = 0, 116 D1 = 1, 117 D2 = 2, 118 D3 = 3, 119 D4 = 4, 120 D5 = 5, 121 D6 = 6, 122 D7 = 7, 123 D8 = 8, 124 D9 = 9, 125 D10 = 10, 126 D11 = 11, 127 D12 = 12, 128 D13 = 13, 129 D14 = 14, 130 D15 = 15, 131 D16 = 16, 132 D17 = 17, 133 D18 = 18, 134 D19 = 19, 135 D20 = 20, 136 D21 = 21, 137 D22 = 22, 138 D23 = 23, 139 D24 = 24, 140 D25 = 25, 141 D26 = 26, 142 D27 = 27, 143 D28 = 28, 144 D29 = 29, 145 D30 = 30, 146 D31 = 31, 147 kNumberOfDRegisters = 32, 148 kNoDRegister = -1, 149 }; 150 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 151 152 // Values for FP SRegisters - single precision floating point. 153 enum SRegister { 154 S0 = 0, 155 S1 = 1, 156 S2 = 2, 157 S3 = 3, 158 S4 = 4, 159 S5 = 5, 160 S6 = 6, 161 S7 = 7, 162 S8 = 8, 163 S9 = 9, 164 S10 = 10, 165 S11 = 11, 166 S12 = 12, 167 S13 = 13, 168 S14 = 14, 169 S15 = 15, 170 S16 = 16, 171 S17 = 17, 172 S18 = 18, 173 S19 = 19, 174 S20 = 20, 175 S21 = 21, 176 S22 = 22, 177 S23 = 23, 178 S24 = 24, 179 S25 = 25, 180 S26 = 26, 181 S27 = 27, 182 S28 = 28, 183 S29 = 29, 184 S30 = 30, 185 S31 = 31, 186 kNumberOfSRegisters = 32, 187 kNoSRegister = -1, 188 }; 189 std::ostream& operator<<(std::ostream& os, const SRegister& rhs); 190 191 } // namespace arm64 192 } // namespace art 193 194 #endif // ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 195