1#include "arm_arch.h"
2
3.text
4.code	32
5
6.align	5
7.global	_armv7_neon_probe
8.type	_armv7_neon_probe,%function
9_armv7_neon_probe:
10	.byte	0xf0,0x01,0x60,0xf2	@ vorr	q8,q8,q8
11	.byte	0x1e,0xff,0x2f,0xe1	@ bx	lr
12.size	_armv7_neon_probe,.-_armv7_neon_probe
13
14.global	_armv7_tick
15.type	_armv7_tick,%function
16_armv7_tick:
17	mrrc	p15,1,r0,r1,c14		@ CNTVCT
18#if __ARM_ARCH__>=5
19	bx	lr
20#else
21	.word	0xe12fff1e		@ bx	lr
22#endif
23.size	_armv7_tick,.-_armv7_tick
24
25.global	_armv8_aes_probe
26.type	_armv8_aes_probe,%function
27_armv8_aes_probe:
28	.byte	0x00,0x03,0xb0,0xf3	@ aese.8	q0,q0
29	.byte	0x1e,0xff,0x2f,0xe1	@ bx	lr
30.size	_armv8_aes_probe,.-_armv8_aes_probe
31
32.global	_armv8_sha1_probe
33.type	_armv8_sha1_probe,%function
34_armv8_sha1_probe:
35	.byte	0x40,0x0c,0x00,0xf2	@ sha1c.32	q0,q0,q0
36	.byte	0x1e,0xff,0x2f,0xe1	@ bx	lr
37.size	_armv8_sha1_probe,.-_armv8_sha1_probe
38
39.global	_armv8_sha256_probe
40.type	_armv8_sha256_probe,%function
41_armv8_sha256_probe:
42	.byte	0x40,0x0c,0x00,0xf3	@ sha256h.32	q0,q0,q0
43	.byte	0x1e,0xff,0x2f,0xe1	@ bx lr
44.size	_armv8_sha256_probe,.-_armv8_sha256_probe
45.global	_armv8_pmull_probe
46.type	_armv8_pmull_probe,%function
47_armv8_pmull_probe:
48	.byte	0x00,0x0e,0xa0,0xf2	@ vmull.p64	q0,d0,d0
49	.byte	0x1e,0xff,0x2f,0xe1	@ bx	lr
50.size	_armv8_pmull_probe,.-_armv8_pmull_probe
51
52.align	5
53.global	OPENSSL_atomic_add
54.type	OPENSSL_atomic_add,%function
55OPENSSL_atomic_add:
56#if __ARM_ARCH__>=6
57.Ladd:	ldrex	r2,[r0]
58	add	r3,r2,r1
59	strex	r2,r3,[r0]
60	cmp	r2,#0
61	bne	.Ladd
62	mov	r0,r3
63	bx	lr
64#else
65	stmdb	sp!,{r4-r6,lr}
66	ldr	r2,.Lspinlock
67	adr	r3,.Lspinlock
68	mov	r4,r0
69	mov	r5,r1
70	add	r6,r3,r2	@ &spinlock
71	b	.+8
72.Lspin:	bl	sched_yield
73	mov	r0,#-1
74	swp	r0,r0,[r6]
75	cmp	r0,#0
76	bne	.Lspin
77
78	ldr	r2,[r4]
79	add	r2,r2,r5
80	str	r2,[r4]
81	str	r0,[r6]		@ release spinlock
82	ldmia	sp!,{r4-r6,lr}
83	tst	lr,#1
84	moveq	pc,lr
85	.word	0xe12fff1e	@ bx	lr
86#endif
87.size	OPENSSL_atomic_add,.-OPENSSL_atomic_add
88
89.global	OPENSSL_cleanse
90.type	OPENSSL_cleanse,%function
91OPENSSL_cleanse:
92	eor	ip,ip,ip
93	cmp	r1,#7
94	subhs	r1,r1,#4
95	bhs	.Lot
96	cmp	r1,#0
97	beq	.Lcleanse_done
98.Little:
99	strb	ip,[r0],#1
100	subs	r1,r1,#1
101	bhi	.Little
102	b	.Lcleanse_done
103
104.Lot:	tst	r0,#3
105	beq	.Laligned
106	strb	ip,[r0],#1
107	sub	r1,r1,#1
108	b	.Lot
109.Laligned:
110	str	ip,[r0],#4
111	subs	r1,r1,#4
112	bhs	.Laligned
113	adds	r1,r1,#4
114	bne	.Little
115.Lcleanse_done:
116#if __ARM_ARCH__>=5
117	bx	lr
118#else
119	tst	lr,#1
120	moveq	pc,lr
121	.word	0xe12fff1e	@ bx	lr
122#endif
123.size	OPENSSL_cleanse,.-OPENSSL_cleanse
124
125.global	OPENSSL_wipe_cpu
126.type	OPENSSL_wipe_cpu,%function
127OPENSSL_wipe_cpu:
128	ldr	r0,.LOPENSSL_armcap
129	adr	r1,.LOPENSSL_armcap
130	ldr	r0,[r1,r0]
131	eor	r2,r2,r2
132	eor	r3,r3,r3
133	eor	ip,ip,ip
134	tst	r0,#1
135	beq	.Lwipe_done
136	.byte	0x50,0x01,0x00,0xf3	@ veor	q0, q0, q0
137	.byte	0x52,0x21,0x02,0xf3	@ veor	q1, q1, q1
138	.byte	0x54,0x41,0x04,0xf3	@ veor	q2, q2, q2
139	.byte	0x56,0x61,0x06,0xf3	@ veor	q3, q3, q3
140	.byte	0xf0,0x01,0x40,0xf3	@ veor	q8, q8, q8
141	.byte	0xf2,0x21,0x42,0xf3	@ veor	q9, q9, q9
142	.byte	0xf4,0x41,0x44,0xf3	@ veor	q10, q10, q10
143	.byte	0xf6,0x61,0x46,0xf3	@ veor	q11, q11, q11
144	.byte	0xf8,0x81,0x48,0xf3	@ veor	q12, q12, q12
145	.byte	0xfa,0xa1,0x4a,0xf3	@ veor	q13, q13, q13
146	.byte	0xfc,0xc1,0x4c,0xf3	@ veor	q14, q14, q14
147	.byte	0xfe,0xe1,0x4e,0xf3	@ veor	q14, q14, q14
148.Lwipe_done:
149	mov	r0,sp
150#if __ARM_ARCH__>=5
151	bx	lr
152#else
153	tst	lr,#1
154	moveq	pc,lr
155	.word	0xe12fff1e	@ bx	lr
156#endif
157.size	OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
158
159.global	OPENSSL_instrument_bus
160.type	OPENSSL_instrument_bus,%function
161OPENSSL_instrument_bus:
162	eor	r0,r0,r0
163#if __ARM_ARCH__>=5
164	bx	lr
165#else
166	tst	lr,#1
167	moveq	pc,lr
168	.word	0xe12fff1e	@ bx	lr
169#endif
170.size	OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
171
172.global	OPENSSL_instrument_bus2
173.type	OPENSSL_instrument_bus2,%function
174OPENSSL_instrument_bus2:
175	eor	r0,r0,r0
176#if __ARM_ARCH__>=5
177	bx	lr
178#else
179	tst	lr,#1
180	moveq	pc,lr
181	.word	0xe12fff1e	@ bx	lr
182#endif
183.size	OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
184
185.align	5
186.LOPENSSL_armcap:
187.word	OPENSSL_armcap_P-.LOPENSSL_armcap
188#if __ARM_ARCH__>=6
189.align	5
190#else
191.Lspinlock:
192.word	atomic_add_spinlock-.Lspinlock
193.align	5
194
195.data
196.align	2
197atomic_add_spinlock:
198.word	0
199#endif
200
201.comm	OPENSSL_armcap_P,4,4
202.hidden	OPENSSL_armcap_P
203