android-5.1.0_r1/s

/*
 * Copyright (c) 2011 Intel Corporation. All Rights Reserved.
 * Copyright (c) Imagination Technologies Limited, UK
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */


/*!
******************************************************************************
@file   : /work/sim/msvdx/register_includes/msvdx_core_regs_io2.h

@brief

@Author <Autogenerated>

<b>Description:</b>\n
                This file contains the MSVDX_CORE_REGS_IO2_H Defintions.

<b>Platform:</b>\n
                ?

@Version
                1.0

******************************************************************************/

#if !defined (__MSVDX_CORE_REGS_IO2_H__)
#define __MSVDX_CORE_REGS_IO2_H__

#ifdef __cplusplus
extern "C" {
#endif


#define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_OFFSET          (0x0094)
#define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_STRIDE          (4)
#define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_NO_ENTRIES              (4)

// MSVDX_CORE     CR_MMU_DIR_LIST_BASE     CR_MMU_DIR_LIST_BASE_ADDR
#define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_CR_MMU_DIR_LIST_BASE_ADDR_MASK          (0xFFFFF000)
#define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_CR_MMU_DIR_LIST_BASE_ADDR_LSBMASK               (0x000FFFFF)
#define MSVDX_CORE_CR_MMU_DIR_LIST_BASE_CR_MMU_DIR_LIST_BASE_ADDR_SHIFT         (12)

#define MSVDX_CORE_CR_MMU_TILE_OFFSET           (0x00D4)
#define MSVDX_CORE_CR_MMU_TILE_STRIDE           (4)
#define MSVDX_CORE_CR_MMU_TILE_NO_ENTRIES               (4)

// MSVDX_CORE     CR_MMU_TILE     CR_TILE_MIN_ADDR
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MIN_ADDR_MASK            (0x00000FFF)
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MIN_ADDR_LSBMASK         (0x00000FFF)
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MIN_ADDR_SHIFT           (0)

// MSVDX_CORE     CR_MMU_TILE     CR_TILE_MAX_ADDR
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MAX_ADDR_MASK            (0x00FFF000)
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MAX_ADDR_LSBMASK         (0x00000FFF)
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_MAX_ADDR_SHIFT           (12)

// MSVDX_CORE     CR_MMU_TILE     CR_TILE_CFG
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_CFG_MASK         (0x0F000000)
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_CFG_LSBMASK              (0x0000000F)
#define MSVDX_CORE_CR_MMU_TILE_CR_TILE_CFG_SHIFT                (24)

#define MSVDX_CORE_CR_MSVDX_CONTROL_OFFSET              (0x0000)

// MSVDX_CORE     CR_MSVDX_CONTROL     CR_ENDIAN
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_ENDIAN_MASK              (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_ENDIAN_LSBMASK           (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_ENDIAN_SHIFT             (0)

// MSVDX_CORE     CR_MSVDX_CONTROL     CR_MSVDX_SOFT_RESET
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_MASK            (0x00000100)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_SOFT_RESET_SHIFT           (8)

// MSVDX_CORE     CR_MSVDX_CONTROL     DMAC_CH0_SELECT
#define MSVDX_CORE_CR_MSVDX_CONTROL_DMAC_CH0_SELECT_MASK                (0x00001000)
#define MSVDX_CORE_CR_MSVDX_CONTROL_DMAC_CH0_SELECT_LSBMASK             (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_DMAC_CH0_SELECT_SHIFT               (12)

// MSVDX_CORE     CR_MSVDX_CONTROL     CR_MSVDX_FE_SOFT_RESET
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_MASK         (0x00010000)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_LSBMASK              (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_FE_SOFT_RESET_SHIFT                (16)

// MSVDX_CORE     CR_MSVDX_CONTROL     CR_MSVDX_BE_SOFT_RESET
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_MASK         (0x00100000)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_LSBMASK              (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_BE_SOFT_RESET_SHIFT                (20)

// MSVDX_CORE     CR_MSVDX_CONTROL     CR_MSVDX_VDMC_VDEB_SOFT_RESET
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VDMC_VDEB_SOFT_RESET_MASK          (0x00200000)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VDMC_VDEB_SOFT_RESET_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VDMC_VDEB_SOFT_RESET_SHIFT         (21)

// MSVDX_CORE     CR_MSVDX_CONTROL     CR_MSVDX_VEC_MEMIF_SOFT_RESET
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_MASK          (0x01000000)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_MEMIF_SOFT_RESET_SHIFT         (24)

// MSVDX_CORE     CR_MSVDX_CONTROL     CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_MASK             (0x10000000)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_LSBMASK          (0x00000001)
#define MSVDX_CORE_CR_MSVDX_CONTROL_CR_MSVDX_VEC_RENDEC_DEC_SOFT_RESET_SHIFT            (28)

#define MSVDX_CORE_CR_MSVDX_INTERNAL_OFFSET             (0x0004)

// MSVDX_CORE     CR_MSVDX_INTERNAL     CR_MPEG4_DP_SUPPORTED
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_DP_SUPPORTED_MASK         (0x40000000)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_DP_SUPPORTED_LSBMASK              (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_DP_SUPPORTED_SHIFT                (30)

// MSVDX_CORE     CR_MSVDX_INTERNAL     CR_JPEG_SUPPORTED
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_JPEG_SUPPORTED_MASK             (0x20000000)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_JPEG_SUPPORTED_LSBMASK          (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_JPEG_SUPPORTED_SHIFT            (29)

// MSVDX_CORE     CR_MSVDX_INTERNAL     CR_WMV_SUPPORTED
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_WMV_SUPPORTED_MASK              (0x10000000)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_WMV_SUPPORTED_LSBMASK           (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_WMV_SUPPORTED_SHIFT             (28)

// MSVDX_CORE     CR_MSVDX_INTERNAL     CR_VC1_SUPPORTED
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_VC1_SUPPORTED_MASK              (0x08000000)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_VC1_SUPPORTED_LSBMASK           (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_VC1_SUPPORTED_SHIFT             (27)

// MSVDX_CORE     CR_MSVDX_INTERNAL     CR_H264_SUPPORTED
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_H264_SUPPORTED_MASK             (0x04000000)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_H264_SUPPORTED_LSBMASK          (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_H264_SUPPORTED_SHIFT            (26)

// MSVDX_CORE     CR_MSVDX_INTERNAL     CR_MPEG4_SUPPORTED
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_SUPPORTED_MASK            (0x02000000)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_SUPPORTED_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG4_SUPPORTED_SHIFT           (25)

// MSVDX_CORE     CR_MSVDX_INTERNAL     CR_MPEG2_SUPPORTED
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG2_SUPPORTED_MASK            (0x01000000)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG2_SUPPORTED_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MPEG2_SUPPORTED_SHIFT           (24)

// MSVDX_CORE     CR_MSVDX_INTERNAL     CR_MSVDX_INTERNAL
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MSVDX_INTERNAL_MASK             (0x00FFFFFF)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MSVDX_INTERNAL_LSBMASK          (0x00FFFFFF)
#define MSVDX_CORE_CR_MSVDX_INTERNAL_CR_MSVDX_INTERNAL_SHIFT            (0)

#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_OFFSET             (0x0008)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_END_OF_SLICE
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_END_OF_SLICE_MASK           (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_END_OF_SLICE_LSBMASK                (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_END_OF_SLICE_SHIFT          (0)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_ERROR_DETECTED_SR
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_SR_MASK              (0x00000002)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_SR_LSBMASK           (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_SR_SHIFT             (1)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_ERROR_DETECTED_ENTDEC
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_ENTDEC_MASK          (0x00000004)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_ENTDEC_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_ERROR_DETECTED_ENTDEC_SHIFT         (2)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_RENDEC_ERROR
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_ERROR_MASK           (0x00000008)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_ERROR_LSBMASK                (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_ERROR_SHIFT          (3)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_RENDEC_OVERFLOW
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_OVERFLOW_MASK                (0x00000010)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_OVERFLOW_LSBMASK             (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_OVERFLOW_SHIFT               (4)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_RENDEC_UNDERFLOW
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_UNDERFLOW_MASK               (0x00000020)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_UNDERFLOW_LSBMASK            (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_UNDERFLOW_SHIFT              (5)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_RENDEC_MTXBLOCK
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_MTXBLOCK_MASK                (0x00000040)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_MTXBLOCK_LSBMASK             (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_MTXBLOCK_SHIFT               (6)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_RENDEC_END_OF_SLICE
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_END_OF_SLICE_MASK            (0x00000080)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_END_OF_SLICE_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_END_OF_SLICE_SHIFT           (7)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_MMU_FAULT_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK              (0x00000F00)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_LSBMASK           (0x0000000F)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_SHIFT             (8)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_FE_WDT_CM0
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM0_MASK         (0x00001000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM0_LSBMASK              (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM0_SHIFT                (12)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_FE_WDT_CM1
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM1_MASK         (0x00002000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM1_LSBMASK              (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_FE_WDT_CM1_SHIFT                (13)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_MTX_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_MASK            (0x00004000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_SHIFT           (14)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_MTX_GPIO_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_GPIO_IRQ_MASK               (0x00008000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_GPIO_IRQ_LSBMASK            (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_GPIO_IRQ_SHIFT              (15)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VDMC_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDMC_IRQ_MASK           (0x00010000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDMC_IRQ_LSBMASK                (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDMC_IRQ_SHIFT          (16)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VDEB_PICTURE_DONE_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_PICTURE_DONE_IRQ_MASK              (0x00020000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_PICTURE_DONE_IRQ_LSBMASK           (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_PICTURE_DONE_IRQ_SHIFT             (17)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VDEB_SLICE_DONE_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_SLICE_DONE_IRQ_MASK                (0x00040000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_SLICE_DONE_IRQ_LSBMASK             (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_SLICE_DONE_IRQ_SHIFT               (18)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VDEB_FLUSH_DONE_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FLUSH_DONE_IRQ_MASK                (0x00080000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FLUSH_DONE_IRQ_LSBMASK             (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FLUSH_DONE_IRQ_SHIFT               (19)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_DMAC_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_DMAC_IRQ_MASK           (0x00700000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_DMAC_IRQ_LSBMASK                (0x00000007)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_DMAC_IRQ_SHIFT          (20)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VDEB_FAULT_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FAULT_IRQ_MASK             (0x00800000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FAULT_IRQ_LSBMASK          (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VDEB_FAULT_IRQ_SHIFT            (23)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_SYS_COMMAND_TIMEOUT_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_COMMAND_TIMEOUT_IRQ_MASK            (0x01000000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_COMMAND_TIMEOUT_IRQ_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_COMMAND_TIMEOUT_IRQ_SHIFT           (24)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_SYS_READ_TIMEOUT_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_READ_TIMEOUT_IRQ_MASK               (0x02000000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_READ_TIMEOUT_IRQ_LSBMASK            (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_READ_TIMEOUT_IRQ_SHIFT              (25)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_MTX_COMMAND_TIMEOUT_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_COMMAND_TIMEOUT_IRQ_MASK            (0x04000000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_COMMAND_TIMEOUT_IRQ_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_COMMAND_TIMEOUT_IRQ_SHIFT           (26)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_MTX_READ_TIMEOUT_IRQ
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_READ_TIMEOUT_IRQ_MASK               (0x08000000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_READ_TIMEOUT_IRQ_LSBMASK            (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_MTX_READ_TIMEOUT_IRQ_SHIFT              (27)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_SYS_WDT
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_WDT_MASK            (0x10000000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_WDT_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_SYS_WDT_SHIFT           (28)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_BE_WDT_CM0
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM0_MASK         (0x20000000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM0_LSBMASK              (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM0_SHIFT                (29)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_BE_WDT_CM1
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM1_MASK         (0x40000000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM1_LSBMASK              (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_BE_WDT_CM1_SHIFT                (30)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_STATUS     CR_VEC_RENDEC_SLICE_SKIPPED
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_SLICE_SKIPPED_MASK           (0x80000000)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_SLICE_SKIPPED_LSBMASK                (0x00000001)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_STATUS_CR_VEC_RENDEC_SLICE_SKIPPED_SHIFT          (31)

#define MSVDX_CORE_CR_MSVDX_INTERRUPT_CLEAR_OFFSET              (0x000C)

// MSVDX_CORE     CR_MSVDX_INTERRUPT_CLEAR     CR_IRQ_CLEAR
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_CLEAR_CR_IRQ_CLEAR_MASK           (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_CLEAR_CR_IRQ_CLEAR_LSBMASK                (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_INTERRUPT_CLEAR_CR_IRQ_CLEAR_SHIFT          (0)

#define MSVDX_CORE_CR_MSVDX_HOST_INTERRUPT_ENABLE_OFFSET                (0x0010)

// MSVDX_CORE     CR_MSVDX_HOST_INTERRUPT_ENABLE     CR_HOST_IRQ_ENABLE
#define MSVDX_CORE_CR_MSVDX_HOST_INTERRUPT_ENABLE_CR_HOST_IRQ_ENABLE_MASK               (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_HOST_INTERRUPT_ENABLE_CR_HOST_IRQ_ENABLE_LSBMASK            (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_HOST_INTERRUPT_ENABLE_CR_HOST_IRQ_ENABLE_SHIFT              (0)

#define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT1_ENABLE_OFFSET                (0x0014)

// MSVDX_CORE     CR_MSVDX_MTX_INTERRUPT1_ENABLE     CR_MTX_IRQ1_ENABLE
#define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT1_ENABLE_CR_MTX_IRQ1_ENABLE_MASK               (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT1_ENABLE_CR_MTX_IRQ1_ENABLE_LSBMASK            (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT1_ENABLE_CR_MTX_IRQ1_ENABLE_SHIFT              (0)

#define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT2_ENABLE_OFFSET                (0x0018)

// MSVDX_CORE     CR_MSVDX_MTX_INTERRUPT2_ENABLE     CR_MTX_IRQ2_ENABLE
#define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT2_ENABLE_CR_MTX_IRQ2_ENABLE_MASK               (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT2_ENABLE_CR_MTX_IRQ2_ENABLE_LSBMASK            (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_MTX_INTERRUPT2_ENABLE_CR_MTX_IRQ2_ENABLE_SHIFT              (0)

#define MSVDX_CORE_CR_MSVDX_RSVD0_OFFSET                (0x001C)

// MSVDX_CORE     CR_MSVDX_RSVD0     CR_RSVD0
#define MSVDX_CORE_CR_MSVDX_RSVD0_CR_RSVD0_MASK         (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_RSVD0_CR_RSVD0_LSBMASK              (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_RSVD0_CR_RSVD0_SHIFT                (0)

#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_OFFSET               (0x0020)

// MSVDX_CORE     CR_MSVDX_MAN_CLK_ENABLE     CR_CORE_MAN_CLK_ENABLE
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_MASK          (0x00000001)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_CORE_MAN_CLK_ENABLE_SHIFT         (0)

// MSVDX_CORE     CR_MSVDX_MAN_CLK_ENABLE     CR_VDEB_PROCESS_MAN_CLK_ENABLE
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_MASK          (0x00000002)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_PROCESS_MAN_CLK_ENABLE_SHIFT         (1)

// MSVDX_CORE     CR_MSVDX_MAN_CLK_ENABLE     CR_VDEB_ACCESS_MAN_CLK_ENABLE
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_MASK           (0x00000004)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_LSBMASK                (0x00000001)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDEB_ACCESS_MAN_CLK_ENABLE_SHIFT          (2)

// MSVDX_CORE     CR_MSVDX_MAN_CLK_ENABLE     CR_VDMC_MAN_CLK_ENABLE
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_MASK          (0x00000008)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VDMC_MAN_CLK_ENABLE_SHIFT         (3)

// MSVDX_CORE     CR_MSVDX_MAN_CLK_ENABLE     CR_VEC_ENTDEC_MAN_CLK_ENABLE
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_MASK            (0x00000010)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ENTDEC_MAN_CLK_ENABLE_SHIFT           (4)

// MSVDX_CORE     CR_MSVDX_MAN_CLK_ENABLE     CR_VEC_ITRANS_MAN_CLK_ENABLE
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_MASK            (0x00000020)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_VEC_ITRANS_MAN_CLK_ENABLE_SHIFT           (5)

// MSVDX_CORE     CR_MSVDX_MAN_CLK_ENABLE     CR_MTX_MAN_CLK_ENABLE
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_MASK           (0x00000040)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_LSBMASK                (0x00000001)
#define MSVDX_CORE_CR_MSVDX_MAN_CLK_ENABLE_CR_MTX_MAN_CLK_ENABLE_SHIFT          (6)

#define MSVDX_CORE_CR_MSVDX_RTM_OFFSET          (0x0024)

// MSVDX_CORE     CR_MSVDX_RTM     CR_RTM_B_BUS
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_B_BUS_MASK               (0xFF000000)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_B_BUS_LSBMASK            (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_B_BUS_SHIFT              (24)

// MSVDX_CORE     CR_MSVDX_RTM     CR_RTM_A_BUS
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_A_BUS_MASK               (0x00FF0000)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_A_BUS_LSBMASK            (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_A_BUS_SHIFT              (16)

// MSVDX_CORE     CR_MSVDX_RTM     CR_RTM_SELECT_B_MODULE
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_MODULE_MASK             (0x00000300)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_MODULE_LSBMASK          (0x00000003)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_MODULE_SHIFT            (8)

// MSVDX_CORE     CR_MSVDX_RTM     CR_RTM_SELECT_A_MODULE
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_MODULE_MASK             (0x000000C0)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_MODULE_LSBMASK          (0x00000003)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_MODULE_SHIFT            (6)

// MSVDX_CORE     CR_MSVDX_RTM     CR_RTM_SELECT_B
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_MASK            (0x00000038)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_LSBMASK         (0x00000007)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_B_SHIFT           (3)

// MSVDX_CORE     CR_MSVDX_RTM     CR_RTM_SELECT_A
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_MASK            (0x00000007)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_LSBMASK         (0x00000007)
#define MSVDX_CORE_CR_MSVDX_RTM_CR_RTM_SELECT_A_SHIFT           (0)

#define MSVDX_CORE_CR_MSVDX_COMMAND_SPACE_OFFSET                (0x0028)

// MSVDX_CORE     CR_MSVDX_COMMAND_SPACE     CR_MSVDX_CMD_BUFFER_SPACE
#define MSVDX_CORE_CR_MSVDX_COMMAND_SPACE_CR_MSVDX_CMD_BUFFER_SPACE_MASK                (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_COMMAND_SPACE_CR_MSVDX_CMD_BUFFER_SPACE_LSBMASK             (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_COMMAND_SPACE_CR_MSVDX_CMD_BUFFER_SPACE_SHIFT               (0)

#define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_OFFSET         (0x002C)

// MSVDX_CORE     CR_MSVDX_RENDEC_SPACE     CR_MSVDX_RENDEC_WRITE_SPACE
#define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_WRITE_SPACE_MASK               (0x00000001)
#define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_WRITE_SPACE_LSBMASK            (0x00000001)
#define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_WRITE_SPACE_SHIFT              (0)

// MSVDX_CORE     CR_MSVDX_RENDEC_SPACE     CR_MSVDX_RENDEC_READ_AVAILABLE
#define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_READ_AVAILABLE_MASK            (0x00000010)
#define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_READ_AVAILABLE_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MSVDX_RENDEC_SPACE_CR_MSVDX_RENDEC_READ_AVAILABLE_SHIFT           (4)

#define MSVDX_CORE_CR_MSVDX_CORE_ID_OFFSET              (0x0030)

// MSVDX_CORE     CR_MSVDX_CORE_ID     CR_CR_MSVDX_CORE_CONFIG
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CR_MSVDX_CORE_CONFIG_MASK                (0x0000FFFF)
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CR_MSVDX_CORE_CONFIG_LSBMASK             (0x0000FFFF)
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CR_MSVDX_CORE_CONFIG_SHIFT               (0)

// MSVDX_CORE     CR_MSVDX_CORE_ID     CR_CORE_ID
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CORE_ID_MASK             (0x00FF0000)
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CORE_ID_LSBMASK          (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_CORE_ID_SHIFT            (16)

// MSVDX_CORE     CR_MSVDX_CORE_ID     CR_GROUP_ID
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_GROUP_ID_MASK            (0xFF000000)
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_GROUP_ID_LSBMASK         (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_CORE_ID_CR_GROUP_ID_SHIFT           (24)

#define MSVDX_CORE_CR_MSVDX_CORE_REV_OFFSET             (0x0040)

// MSVDX_CORE     CR_MSVDX_CORE_REV     CR_MSVDX_MAINT_REV
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAINT_REV_MASK            (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAINT_REV_LSBMASK         (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAINT_REV_SHIFT           (0)

// MSVDX_CORE     CR_MSVDX_CORE_REV     CR_MSVDX_MINOR_REV
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MINOR_REV_MASK            (0x0000FF00)
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MINOR_REV_LSBMASK         (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MINOR_REV_SHIFT           (8)

// MSVDX_CORE     CR_MSVDX_CORE_REV     CR_MSVDX_MAJOR_REV
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAJOR_REV_MASK            (0x00FF0000)
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAJOR_REV_LSBMASK         (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_MAJOR_REV_SHIFT           (16)

// MSVDX_CORE     CR_MSVDX_CORE_REV     CR_MSVDX_DESIGNER
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_DESIGNER_MASK             (0xFF000000)
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_DESIGNER_LSBMASK          (0x000000FF)
#define MSVDX_CORE_CR_MSVDX_CORE_REV_CR_MSVDX_DESIGNER_SHIFT            (24)

#define MSVDX_CORE_CR_MSVDX_CORE_DES1_OFFSET            (0x0050)

// MSVDX_CORE     CR_MSVDX_CORE_DES1     CR_MSVDX_DESIGNER1
#define MSVDX_CORE_CR_MSVDX_CORE_DES1_CR_MSVDX_DESIGNER1_MASK           (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_CORE_DES1_CR_MSVDX_DESIGNER1_LSBMASK                (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_CORE_DES1_CR_MSVDX_DESIGNER1_SHIFT          (0)

#define MSVDX_CORE_CR_MSVDX_CORE_DES2_OFFSET            (0x0060)

// MSVDX_CORE     CR_MSVDX_CORE_DES2     CR_MSVDX_DESIGNER2
#define MSVDX_CORE_CR_MSVDX_CORE_DES2_CR_MSVDX_DESIGNER2_MASK           (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_CORE_DES2_CR_MSVDX_DESIGNER2_LSBMASK                (0xFFFFFFFF)
#define MSVDX_CORE_CR_MSVDX_CORE_DES2_CR_MSVDX_DESIGNER2_SHIFT          (0)

#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_OFFSET               (0x0064)

// MSVDX_CORE     CR_FE_MSVDX_WDT_CONTROL     FE_WDT_ENABLE
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ENABLE_MASK           (0x00010000)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ENABLE_LSBMASK                (0x00000001)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ENABLE_SHIFT          (16)

// MSVDX_CORE     CR_FE_MSVDX_WDT_CONTROL     FE_WDT_ACTION1
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION1_MASK          (0x00003000)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION1_LSBMASK               (0x00000003)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION1_SHIFT         (12)

// MSVDX_CORE     CR_FE_MSVDX_WDT_CONTROL     FE_WDT_ACTION0
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION0_MASK          (0x00000100)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION0_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_ACTION0_SHIFT         (8)

// MSVDX_CORE     CR_FE_MSVDX_WDT_CONTROL     FE_WDT_CLEAR_SELECT
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLEAR_SELECT_MASK             (0x00000030)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLEAR_SELECT_LSBMASK          (0x00000003)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLEAR_SELECT_SHIFT            (4)

// MSVDX_CORE     CR_FE_MSVDX_WDT_CONTROL     FE_WDT_CLKDIV_SELECT
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLKDIV_SELECT_MASK            (0x00000007)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLKDIV_SELECT_LSBMASK         (0x00000007)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_CONTROL_FE_WDT_CLKDIV_SELECT_SHIFT           (0)

#define MSVDX_CORE_CR_FE_MSVDX_WDTIMER_OFFSET           (0x0068)

// MSVDX_CORE     CR_FE_MSVDX_WDTIMER     FE_WDT_COUNTER
#define MSVDX_CORE_CR_FE_MSVDX_WDTIMER_FE_WDT_COUNTER_MASK              (0x0000FFFF)
#define MSVDX_CORE_CR_FE_MSVDX_WDTIMER_FE_WDT_COUNTER_LSBMASK           (0x0000FFFF)
#define MSVDX_CORE_CR_FE_MSVDX_WDTIMER_FE_WDT_COUNTER_SHIFT             (0)

#define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_OFFSET          (0x006C)

// MSVDX_CORE     CR_FE_MSVDX_WDT_COMPAREMATCH     FE_WDT_CM1
#define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM1_MASK         (0xFFFF0000)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM1_LSBMASK              (0x0000FFFF)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM1_SHIFT                (16)

// MSVDX_CORE     CR_FE_MSVDX_WDT_COMPAREMATCH     FE_WDT_CM0
#define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM0_MASK         (0x0000FFFF)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM0_LSBMASK              (0x0000FFFF)
#define MSVDX_CORE_CR_FE_MSVDX_WDT_COMPAREMATCH_FE_WDT_CM0_SHIFT                (0)

#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_OFFSET               (0x0070)

// MSVDX_CORE     CR_BE_MSVDX_WDT_CONTROL     BE_WDT_ENABLE
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ENABLE_MASK           (0x00010000)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ENABLE_LSBMASK                (0x00000001)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ENABLE_SHIFT          (16)

// MSVDX_CORE     CR_BE_MSVDX_WDT_CONTROL     BE_WDT_ACTION1
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION1_MASK          (0x00003000)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION1_LSBMASK               (0x00000003)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION1_SHIFT         (12)

// MSVDX_CORE     CR_BE_MSVDX_WDT_CONTROL     BE_WDT_ACTION0
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION0_MASK          (0x00000100)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION0_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_ACTION0_SHIFT         (8)

// MSVDX_CORE     CR_BE_MSVDX_WDT_CONTROL     BE_WDT_CLEAR_SELECT
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLEAR_SELECT_MASK             (0x000000F0)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLEAR_SELECT_LSBMASK          (0x0000000F)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLEAR_SELECT_SHIFT            (4)

// MSVDX_CORE     CR_BE_MSVDX_WDT_CONTROL     BE_WDT_CLKDIV_SELECT
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLKDIV_SELECT_MASK            (0x00000007)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLKDIV_SELECT_LSBMASK         (0x00000007)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_CONTROL_BE_WDT_CLKDIV_SELECT_SHIFT           (0)

#define MSVDX_CORE_CR_BE_MSVDX_WDTIMER_OFFSET           (0x0074)

// MSVDX_CORE     CR_BE_MSVDX_WDTIMER     BE_WDT_COUNTER
#define MSVDX_CORE_CR_BE_MSVDX_WDTIMER_BE_WDT_COUNTER_MASK              (0x0000FFFF)
#define MSVDX_CORE_CR_BE_MSVDX_WDTIMER_BE_WDT_COUNTER_LSBMASK           (0x0000FFFF)
#define MSVDX_CORE_CR_BE_MSVDX_WDTIMER_BE_WDT_COUNTER_SHIFT             (0)

#define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_OFFSET          (0x0078)

// MSVDX_CORE     CR_BE_MSVDX_WDT_COMPAREMATCH     BE_WDT_CM1
#define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM1_MASK         (0xFFFF0000)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM1_LSBMASK              (0x0000FFFF)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM1_SHIFT                (16)

// MSVDX_CORE     CR_BE_MSVDX_WDT_COMPAREMATCH     BE_WDT_CM0
#define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM0_MASK         (0x0000FFFF)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM0_LSBMASK              (0x0000FFFF)
#define MSVDX_CORE_CR_BE_MSVDX_WDT_COMPAREMATCH_BE_WDT_CM0_SHIFT                (0)

#define MSVDX_CORE_CR_MMU_CONTROL0_OFFSET               (0x0080)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_MMU_INVALDC
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_INVALDC_MASK          (0x00000008)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_INVALDC_LSBMASK               (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_INVALDC_SHIFT         (3)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_MMU_FLUSH
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_FLUSH_MASK            (0x00000004)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_FLUSH_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_FLUSH_SHIFT           (2)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_MMU_PAUSE
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_PAUSE_MASK            (0x00000002)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_PAUSE_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_PAUSE_SHIFT           (1)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_MMU_NOREORDER
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_NOREORDER_MASK                (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_NOREORDER_LSBMASK             (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_NOREORDER_SHIFT               (0)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_FLOWRATE_DMAC
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_DMAC_MASK                (0x00000700)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_DMAC_LSBMASK             (0x00000007)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_DMAC_SHIFT               (8)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_FLOWRATE_VEC
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VEC_MASK         (0x00003800)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VEC_LSBMASK              (0x00000007)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VEC_SHIFT                (11)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_FLOWRATE_VDMC
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDMC_MASK                (0x0001C000)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDMC_LSBMASK             (0x00000007)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDMC_SHIFT               (14)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_FLOWRATE_VDEB
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDEB_MASK                (0x000E0000)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDEB_LSBMASK             (0x00000007)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_FLOWRATE_VDEB_SHIFT               (17)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_MMU_BYPASS_DMAC
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_DMAC_MASK              (0x01000000)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_DMAC_LSBMASK           (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_DMAC_SHIFT             (24)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_MMU_BYPASS_VEC
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VEC_MASK               (0x02000000)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VEC_LSBMASK            (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VEC_SHIFT              (25)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_MMU_BYPASS_VDMC
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDMC_MASK              (0x04000000)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDMC_LSBMASK           (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDMC_SHIFT             (26)

// MSVDX_CORE     CR_MMU_CONTROL0     CR_MMU_BYPASS_VDEB
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDEB_MASK              (0x08000000)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDEB_LSBMASK           (0x00000001)
#define MSVDX_CORE_CR_MMU_CONTROL0_CR_MMU_BYPASS_VDEB_SHIFT             (27)

#define MSVDX_CORE_CR_MMU_CONTROL1_OFFSET               (0x0084)

// MSVDX_CORE     CR_MMU_CONTROL1     CR_MMU_TTE_THRESHOLD
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_TTE_THRESHOLD_MASK            (0x00000FFF)
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_TTE_THRESHOLD_LSBMASK         (0x00000FFF)
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_TTE_THRESHOLD_SHIFT           (0)

// MSVDX_CORE     CR_MMU_CONTROL1     CR_MMU_ADT_TTE
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_ADT_TTE_MASK          (0x000FF000)
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_ADT_TTE_LSBMASK               (0x000000FF)
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_ADT_TTE_SHIFT         (12)

// MSVDX_CORE     CR_MMU_CONTROL1     CR_MMU_BEST_COUNT
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_BEST_COUNT_MASK               (0x0FF00000)
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_BEST_COUNT_LSBMASK            (0x000000FF)
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_BEST_COUNT_SHIFT              (20)

// MSVDX_CORE     CR_MMU_CONTROL1     CR_MMU_PAGE_SIZE
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_PAGE_SIZE_MASK                (0xF0000000)
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_PAGE_SIZE_LSBMASK             (0x0000000F)
#define MSVDX_CORE_CR_MMU_CONTROL1_CR_MMU_PAGE_SIZE_SHIFT               (28)

#define MSVDX_CORE_CR_MMU_BANK_INDEX_OFFSET             (0x0088)

// MSVDX_CORE     CR_MMU_BANK_INDEX     CR_MMU_BANK_SELECT
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_MASK            (0x00000002)
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_SHIFT           (1)
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_NO_REPS         (2)
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_SELECT_SIZE            (1)

// MSVDX_CORE     CR_MMU_BANK_INDEX     CR_MMU_BANK_N_INDEX_M
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_MASK         (0x0000C000)
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_LSBMASK              (0x00000003)
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_SHIFT                (14)
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_NO_REPS              (4)
#define MSVDX_CORE_CR_MMU_BANK_INDEX_CR_MMU_BANK_N_INDEX_M_SIZE         (2)

#define MSVDX_CORE_CR_MMU_STATUS_OFFSET         (0x008C)

// MSVDX_CORE     CR_MMU_STATUS     CR_MMU_FAULT_ADDR
#define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_FAULT_ADDR_MASK         (0xFFFFF000)
#define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_FAULT_ADDR_LSBMASK              (0x000FFFFF)
#define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_FAULT_ADDR_SHIFT                (12)

// MSVDX_CORE     CR_MMU_STATUS     CR_MMU_PF_N_RW
#define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_PF_N_RW_MASK            (0x00000001)
#define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_PF_N_RW_LSBMASK         (0x00000001)
#define MSVDX_CORE_CR_MMU_STATUS_CR_MMU_PF_N_RW_SHIFT           (0)

#define MSVDX_CORE_CR_MMU_MEM_REQ_OFFSET                (0x00D0)

// MSVDX_CORE     CR_MMU_MEM_REQ     CR_MEM_REQ_STAT_READS
#define MSVDX_CORE_CR_MMU_MEM_REQ_CR_MEM_REQ_STAT_READS_MASK            (0x000000FF)
#define MSVDX_CORE_CR_MMU_MEM_REQ_CR_MEM_REQ_STAT_READS_LSBMASK         (0x000000FF)
#define MSVDX_CORE_CR_MMU_MEM_REQ_CR_MEM_REQ_STAT_READS_SHIFT           (0)

#define MSVDX_CORE_CR_MTX_DEBUG_OFFSET          (0x00F0)

// MSVDX_CORE     CR_MTX_DEBUG     CR_MTX_LAST_RAM_BANK_SIZE
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_LAST_RAM_BANK_SIZE_MASK          (0x0F000000)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_LAST_RAM_BANK_SIZE_LSBMASK               (0x0000000F)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_LAST_RAM_BANK_SIZE_SHIFT         (24)

// MSVDX_CORE     CR_MTX_DEBUG     CR_MTX_RAM_BANK_SIZE
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANK_SIZE_MASK               (0x000F0000)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANK_SIZE_LSBMASK            (0x0000000F)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANK_SIZE_SHIFT              (16)

// MSVDX_CORE     CR_MTX_DEBUG     CR_MTX_RAM_BANKS
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANKS_MASK           (0x00000F00)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANKS_LSBMASK                (0x0000000F)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_RAM_BANKS_SHIFT          (8)

// MSVDX_CORE     CR_MTX_DEBUG     CR_MTX_DBG_GPIO_OUT
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_OUT_MASK                (0x00000018)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_OUT_LSBMASK             (0x00000003)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_OUT_SHIFT               (3)

// MSVDX_CORE     CR_MTX_DEBUG     CR_MTX_DBG_IS_SLAVE
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_IS_SLAVE_MASK                (0x00000004)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_IS_SLAVE_LSBMASK             (0x00000001)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_IS_SLAVE_SHIFT               (2)

// MSVDX_CORE     CR_MTX_DEBUG     CR_MTX_DBG_GPIO_IN
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_IN_MASK         (0x00000003)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_IN_LSBMASK              (0x00000003)
#define MSVDX_CORE_CR_MTX_DEBUG_CR_MTX_DBG_GPIO_IN_SHIFT                (0)

#define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_OFFSET              (0x00F4)

// MSVDX_CORE     CR_SYS_MSVDX_WDT_CONTROL     SYS_WDT_ENABLE
#define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_ENABLE_MASK         (0x00010000)
#define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_ENABLE_LSBMASK              (0x00000001)
#define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_ENABLE_SHIFT                (16)

// MSVDX_CORE     CR_SYS_MSVDX_WDT_CONTROL     SYS_WDT_CLKDIV_SELECT
#define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_CLKDIV_SELECT_MASK          (0x00000007)
#define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_CLKDIV_SELECT_LSBMASK               (0x00000007)
#define MSVDX_CORE_CR_SYS_MSVDX_WDT_CONTROL_SYS_WDT_CLKDIV_SELECT_SHIFT         (0)

#define MSVDX_CORE_CR_SYS_MSVDX_WDTIMER_OFFSET          (0x00F8)

// MSVDX_CORE     CR_SYS_MSVDX_WDTIMER     SYS_WDT_COUNTER
#define MSVDX_CORE_CR_SYS_MSVDX_WDTIMER_SYS_WDT_COUNTER_MASK            (0x0000FFFF)
#define MSVDX_CORE_CR_SYS_MSVDX_WDTIMER_SYS_WDT_COUNTER_LSBMASK         (0x0000FFFF)
#define MSVDX_CORE_CR_SYS_MSVDX_WDTIMER_SYS_WDT_COUNTER_SHIFT           (0)


#ifdef __cplusplus
}
#endif

#endif /* __MSVDX_CORE_REGS_IO2_H__ */