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Searched refs:TR (Results 1 – 11 of 11) sorted by relevance

/art/compiler/utils/arm/
Dassembler_arm.cc541 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), TR, dest.Int32Value()); in StoreImmediateToThread32()
569 return EmitLoad(this, m_dst, TR, src.Int32Value(), size); in LoadFromThread32()
575 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), TR, offs.Int32Value()); in LoadRawPtrFromThread32()
584 TR, thr_offs.Int32Value()); in CopyRawPtrFromThread32()
597 TR, thr_offs.Int32Value()); in CopyRawPtrToThread32()
607 TR, thr_offs.Int32Value()); in StoreStackOffsetToThread32()
611 StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value()); in StoreStackPointerToThread32()
804 mov(tr.AsArm().AsCoreRegister(), ShifterOperand(TR)); in GetCurrentThread()
809 StoreToOffset(kStoreWord, TR, SP, offset.Int32Value(), AL); in GetCurrentThread()
817 TR, Thread::ExceptionOffset<4>().Int32Value()); in ExceptionPoll()
[all …]
/art/runtime/arch/arm/
Dregisters_arm.h43 TR = 9, // thread register enumerator
Dcontext_arm.cc113 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]); in DoLongJump()
/art/runtime/arch/arm64/
Dregisters_arm64.h59 TR = 18, // ART Thread Register - Managed Runtime (Caller Saved Reg) enumerator
Dcontext_arm64.cc159 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]); in DoLongJump()
/art/compiler/dex/quick/x86/
Dx86_lir.h408 opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \
411 opcode ## 16MR, opcode ## 16AR, opcode ## 16TR, \
415 opcode ## 32MR, opcode ## 32AR, opcode ## 32TR, \
419 opcode ## 64MR, opcode ## 64AR, opcode ## 64TR, \
Dassemble_x86.cc39 { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES …
51 { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODE…
67 { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODE…
83 { kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODE…
/art/compiler/optimizing/
Dcode_generator_arm.cc69 __ ldr(LR, Address(TR, offset)); in EmitNativeCode()
85 __ LoadFromOffset(kLoadWord, PC, TR, in EmitNativeCode()
107 __ ldr(LR, Address(TR, offset)); in EmitNativeCode()
244 blocked_registers[TR] = true; in SetupBlockedRegisters()
274 __ LoadFromOffset(kLoadWord, IP, TR, Thread::StackEndOffset<kArmWordSize>().Int32Value()); in GenerateFrameEntry()
1003 __ ldr(LR, Address(TR, offset)); in VisitNewInstance()
1409 __ ldr(LR, Address(TR, offset)); in VisitArraySet()
1478 __ LoadFromOffset(kLoadWord, card, TR, Thread::CardTableOffset<kArmWordSize>().Int32Value()); in MarkGCCard()
/art/compiler/trampolines/
Dtrampoline_compiler.cc80 __ JumpTo(Arm64ManagedRegister::FromCoreRegister(TR), Offset(offset.Int32Value()), in CreateTrampoline()
/art/compiler/utils/arm64/
Dassembler_arm64.cc630 ___ Mov(reg_x(TR), reg_x(ETR)); in EmitExceptionPoll()
683 ___ Mov(reg_x(ETR), reg_x(TR)); in BuildFrame()
722 ___ Mov(reg_x(TR), reg_x(ETR)); in RemoveFrame()
Dmanaged_register_arm64_test.cc649 EXPECT_TRUE(vixl::x18.Is(Arm64Assembler::reg_x(TR))); in TEST()