| /art/runtime/arch/arm/ |
| D | memcmp16_arm.S | 60 subs r0, r0, ip
62 subs r2, r2, #1
80 subs r0, r0, ip
102 subs r2, r2, #(16 + 2)
133 subs r2, r2, #16
145 subs r2, r2, #2
159 subs r0, r0, ip
170 subs r0, r0, ip
172 subs r2, r2, #1
211 subs r2, r2, #8
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| D | quick_entrypoints_arm.S | 1228 subs ip, r2, #32 @ ip<- r2 - 32
1250 subs ip, r2, #32 @ ip<- r2 - 32
1272 subs ip, r2, #32 @ ip<- r2 - 32
1329 subs r2, #4
1345 subs r2, #4
1356 subs r2, #1
1432 subs r11, r7, r10
1456 subs r10, #2
1468 subs r0, r3, r4
1474 subs r10, #3
[all …]
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| /art/runtime/arch/arm64/ |
| D | memcmp16_arm64.S | 65 subs limit_wd, limit_wd, #1
136 subs limit, limit, #2
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| D | quick_entrypoints_arm64.S | 1663 subs w2, w2, #4
1679 subs w2, w2, #4
1690 subs w2, w2, #1
1750 subs x0, x4, x3
1781 subs w3, w3, #2
1790 subs w4, w4, w5
1793 subs w6, w6, w7
1806 subs w4, w4, w5
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| /art/compiler/utils/arm/ |
| D | assembler_arm32.cc | 68 void Arm32Assembler::subs(Register rd, Register rn, const ShifterOperand& so, in subs() function in art::arm::Arm32Assembler
1286 subs(rd, rn, shifter_op, cond); in AddConstantSetFlags()
1294 subs(rd, rn, ShifterOperand(IP), cond); in AddConstantSetFlags()
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| D | assembler_arm32.h | 48 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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| D | assembler_thumb2.cc | 70 void Thumb2Assembler::subs(Register rd, Register rn, const ShifterOperand& so, in subs() function in art::arm::Thumb2Assembler
2337 subs(rd, rn, shifter_op, cond); in AddConstantSetFlags()
2345 subs(rd, rn, ShifterOperand(IP), cond); in AddConstantSetFlags()
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| D | assembler_thumb2.h | 70 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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| D | assembler_arm.h | 368 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
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| /art/compiler/optimizing/ |
| D | code_generator_arm.cc | 967 __ subs(locations->Out().AsArm().AsRegisterPairLow(), in VisitSub() local
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| /art/compiler/utils/ |
| D | assembler_thumb_test_expected.cc.inc | 23 " 6: 1a88 subs r0, r1, r2\n",
32 " 26: 1e08 subs r0, r1, #0\n",
66 " 3a: 1f48 subs r0, r1, #5\n",
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