Searched refs:DREG (Results 1 – 3 of 3) sorted by relevance
6 ; CHECK: vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[ADDR]]:32]7 ; CHECK: vst1.32 {[[DREG]], [[DREG2]]}, [r0]
142 #define DREG(n) d##n, macro144 REGISTER_CODE_LIST(DREG)146 #undef DREG
276 ; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]]