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/external/llvm/lib/Target/X86/
DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
53 def WriteLoad : SchedWrite;
54 def WriteStore : SchedWrite;
55 def WriteMove : SchedWrite;
59 def WriteZero : SchedWrite;
[all …]
/external/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
58 def WriteALU : SchedWrite;
59 def ReadALU : SchedRead;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
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/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def AttributedStmt : Stmt;
16 def IfStmt : Stmt;
17 def SwitchStmt : Stmt;
18 def WhileStmt : Stmt;
19 def DoStmt : Stmt;
20 def ForStmt : Stmt;
21 def GotoStmt : Stmt;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def Named : Decl<1>;
15 def Namespace : DDecl<Named>, DeclContext;
16 def UsingDirective : DDecl<Named>;
17 def NamespaceAlias : DDecl<Named>;
18 def Label : DDecl<Named>;
19 def Type : DDecl<Named, 1>;
20 def TypedefName : DDecl<Type, 1>;
21 def Typedef : DDecl<TypedefName>;
22 def TypeAlias : DDecl<TypedefName>;
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DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def AbsoluteValue : DiagGroup<"absolute-value">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">;
25 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
26 def GNUAnonymousStruct : DiagGroup<"gnu-anonymous-struct">;
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/external/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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DCommentCommands.td51 def Begin : Command<name> {
56 def End : Command<endCommandName> {
84 def B : InlineCommand<"b">;
85 def C : InlineCommand<"c">;
86 def P : InlineCommand<"p">;
87 def A : InlineCommand<"a">;
88 def E : InlineCommand<"e">;
89 def Em : InlineCommand<"em">;
95 def Brief : BlockCommand<"brief"> { let IsBriefCommand = 1; }
96 def Short : BlockCommand<"short"> { let IsBriefCommand = 1; }
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/external/llvm/test/TableGen/
DNestedForeach.td15 def S#R#M#P : Droid<S, R, M, P>;
21 // CHECK: def C2D0
22 // CHECK: def C2D2
23 // CHECK: def C2D4
24 // CHECK: def C2P0
25 // CHECK: def C2P2
26 // CHECK: def C2P4
27 // CHECK: def C2Q0
28 // CHECK: def C2Q2
29 // CHECK: def C2Q4
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/external/llvm/lib/Target/Mips/
DMipsSchedule.td13 def ALU : FuncUnit;
14 def IMULDIV : FuncUnit;
19 def IIAlu : InstrItinClass;
20 def IIBranch : InstrItinClass;
21 def IIPseudo : InstrItinClass;
23 def II_ABS : InstrItinClass;
24 def II_ADDI : InstrItinClass;
25 def II_ADDIU : InstrItinClass;
26 def II_ADDU : InstrItinClass;
27 def II_ADD_D : InstrItinClass;
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DMipsRegisterInfo.td14 def sub_32 : SubRegIndex<32>;
15 def sub_64 : SubRegIndex<64>;
16 def sub_lo : SubRegIndex<32>;
17 def sub_hi : SubRegIndex<32, 32>;
18 def sub_dsp16_19 : SubRegIndex<4, 16>;
19 def sub_dsp20 : SubRegIndex<1, 20>;
20 def sub_dsp21 : SubRegIndex<1, 21>;
21 def sub_dsp22 : SubRegIndex<1, 22>;
22 def sub_dsp23 : SubRegIndex<1, 23>;
88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
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/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def qhisub : SubRegIndex<64>;
30 def qsub : SubRegIndex<64>;
32 def dsub0 : SubRegIndex<64>;
33 def dsub1 : SubRegIndex<64>;
34 def dsub2 : SubRegIndex<64>;
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DAArch64SchedA57.td15 def CortexA57Model : SchedMachineModel {
27 def A57UnitB : ProcResource<1> { let BufferSize = 8; } // Type B micro-ops
28 def A57UnitI : ProcResource<2> { let BufferSize = 8; } // Type I micro-ops
29 def A57UnitM : ProcResource<1> { let BufferSize = 8; } // Type M micro-ops
30 def A57UnitL : ProcResource<1> { let BufferSize = 8; } // Type L micro-ops
31 def A57UnitS : ProcResource<1> { let BufferSize = 8; } // Type S micro-ops
32 def A57UnitX : ProcResource<1> { let BufferSize = 8; } // Type X micro-ops
33 def A57UnitW : ProcResource<1> { let BufferSize = 8; } // Type W micro-ops
35 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops
53 def : SchedAlias<WriteImm, A57Write_1cyc_1I>;
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/external/llvm/include/llvm/IR/
DIntrinsicsMips.td16 def mips_v2q15_ty: LLVMType<v2i16>;
17 def mips_v4q7_ty: LLVMType<v4i8>;
18 def mips_q31_ty: LLVMType<i32>;
28 def int_mips_addu_qb : GCCBuiltin<"__builtin_mips_addu_qb">,
31 def int_mips_addu_s_qb : GCCBuiltin<"__builtin_mips_addu_s_qb">,
34 def int_mips_subu_qb : GCCBuiltin<"__builtin_mips_subu_qb">,
36 def int_mips_subu_s_qb : GCCBuiltin<"__builtin_mips_subu_s_qb">,
39 def int_mips_addq_ph : GCCBuiltin<"__builtin_mips_addq_ph">,
42 def int_mips_addq_s_ph : GCCBuiltin<"__builtin_mips_addq_s_ph">,
45 def int_mips_subq_ph : GCCBuiltin<"__builtin_mips_subq_ph">,
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DIntrinsicsHexagon.td614 def int_hexagon_SI_to_SXTHI_asrh :
619 def int_hexagon_circ_ldd :
626 def int_hexagon_C2_cmpeq :
631 def int_hexagon_C2_cmpgt :
636 def int_hexagon_C2_cmpgtu :
641 def int_hexagon_C2_cmpeqp :
646 def int_hexagon_C2_cmpgtp :
651 def int_hexagon_C2_cmpgtup :
656 def int_hexagon_A4_rcmpeqi :
661 def int_hexagon_A4_rcmpneqi :
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DIntrinsicsAArch64.td16 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
18 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
19 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
21 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
22 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
23 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
25 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
28 def int_aarch64_clrex : Intrinsic<[]>;
30 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
53 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
55 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
58 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
61 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
62 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
63 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
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DSparcInstrVIS.td59 def FPADD16 : VISInst<0b001010000, "fpadd16">;
60 def FPADD16S : VISInst<0b001010001, "fpadd16s">;
61 def FPADD32 : VISInst<0b001010010, "fpadd32">;
62 def FPADD32S : VISInst<0b001010011, "fpadd32s">;
63 def FPSUB16 : VISInst<0b001010100, "fpsub16">;
64 def FPSUB16S : VISInst<0b001010101, "fpsub16S">;
65 def FPSUB32 : VISInst<0b001010110, "fpsub32">;
66 def FPSUB32S : VISInst<0b001010111, "fpsub32S">;
68 def FPACK16 : VISInst2<0b000111011, "fpack16">;
69 def FPACK32 : VISInst <0b000111010, "fpack32">;
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/external/clang/include/clang/Driver/
DCLCompatOptions.td14 def cl_Group : OptionGroup<"<clang-cl options>">,
17 def cl_compile_Group : OptionGroup<"<clang-cl compile-only options>">,
20 def cl_ignored_Group : OptionGroup<"<clang-cl ignored options>">,
55 def _SLASH_C : CLFlag<"C">, HelpText<"Don't discard comments when preprocessing">,
57 def _SLASH_c : CLFlag<"c">, HelpText<"Compile only">, Alias<c>;
58 def _SLASH_D : CLJoinedOrSeparate<"D">, HelpText<"Define macro">,
60 def _SLASH_E : CLFlag<"E">, HelpText<"Preprocess to stdout">, Alias<E>;
61 def _SLASH_GR : CLFlag<"GR">, HelpText<"Enable emission of RTTI data">;
62 def _SLASH_GR_ : CLFlag<"GR-">, HelpText<"Disable emission of RTTI data">;
63 def _SLASH_GF_ : CLFlag<"GF-">, HelpText<"Disable string pooling">,
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DOptions.td22 def DriverOption : OptionFlag;
25 def LinkerInput : OptionFlag;
30 def NoArgumentUnused : OptionFlag;
34 def Unsupported : OptionFlag;
38 def CoreOption : OptionFlag;
42 def CLOption : OptionFlag;
45 def CC1Option : OptionFlag;
48 def CC1AsOption : OptionFlag;
51 def NoDriverOption : OptionFlag;
58 def CompileOnly_Group : OptionGroup<"<CompileOnly group>">;
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDILIntrinsics.td69 def int_AMDIL_fabs : GCCBuiltin<"__amdil_fabs">, UnaryIntFloat;
70 def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
72 def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">,
74 def int_AMDIL_bit_extract_u32 : GCCBuiltin<"__amdil_ubit_extract">,
76 def int_AMDIL_bit_reverse_u32 : GCCBuiltin<"__amdil_ubit_reverse">,
78 def int_AMDIL_bit_count_i32 : GCCBuiltin<"__amdil_count_bits">,
80 def int_AMDIL_bit_find_first_lo : GCCBuiltin<"__amdil_ffb_lo">,
82 def int_AMDIL_bit_find_first_hi : GCCBuiltin<"__amdil_ffb_hi">,
84 def int_AMDIL_bit_find_first_sgn : GCCBuiltin<"__amdil_ffb_signed">,
86 def int_AMDIL_media_bitalign : GCCBuiltin<"__amdil_bitalign">,
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DSIInstructions.td10 def isSI : Predicate<"Subtarget.device()"
16 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
17 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
18 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
19 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
20 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>;
21 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
22 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
23 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
24 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
[all …]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDILIntrinsics.td69 def int_AMDIL_fabs : GCCBuiltin<"__amdil_fabs">, UnaryIntFloat;
70 def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
72 def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">,
74 def int_AMDIL_bit_extract_u32 : GCCBuiltin<"__amdil_ubit_extract">,
76 def int_AMDIL_bit_reverse_u32 : GCCBuiltin<"__amdil_ubit_reverse">,
78 def int_AMDIL_bit_count_i32 : GCCBuiltin<"__amdil_count_bits">,
80 def int_AMDIL_bit_find_first_lo : GCCBuiltin<"__amdil_ffb_lo">,
82 def int_AMDIL_bit_find_first_hi : GCCBuiltin<"__amdil_ffb_hi">,
84 def int_AMDIL_bit_find_first_sgn : GCCBuiltin<"__amdil_ffb_signed">,
86 def int_AMDIL_media_bitalign : GCCBuiltin<"__amdil_bitalign">,
[all …]
DSIInstructions.td10 def isSI : Predicate<"Subtarget.device()"
16 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
17 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
18 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
19 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
20 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>;
21 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
22 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
23 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
24 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/common/xmlpool/
Dt_options.h55 #define DRI_CONF_NO_RAST(def) \ argument
56 DRI_CONF_OPT_BEGIN(no_rast,bool,def) \
60 #define DRI_CONF_PERFORMANCE_BOXES(def) \ argument
61 DRI_CONF_OPT_BEGIN(performance_boxes,bool,def) \
71 #define DRI_CONF_EXCESS_MIPMAP(def) \ argument
72 DRI_CONF_OPT_BEGIN(excess_mipmap,bool,def) \
80 #define DRI_CONF_TEXTURE_DEPTH(def) \ argument
81 DRI_CONF_OPT_BEGIN_V(texture_depth,enum,def,"0:3") \
90 #define DRI_CONF_DEF_MAX_ANISOTROPY(def,range) \ argument
91 DRI_CONF_OPT_BEGIN_V(def_max_anisotropy,float,def,range) \
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/external/mesa3d/src/mesa/drivers/dri/common/xmlpool/
Dt_options.h55 #define DRI_CONF_NO_RAST(def) \ argument
56 DRI_CONF_OPT_BEGIN(no_rast,bool,def) \
60 #define DRI_CONF_PERFORMANCE_BOXES(def) \ argument
61 DRI_CONF_OPT_BEGIN(performance_boxes,bool,def) \
71 #define DRI_CONF_EXCESS_MIPMAP(def) \ argument
72 DRI_CONF_OPT_BEGIN(excess_mipmap,bool,def) \
80 #define DRI_CONF_TEXTURE_DEPTH(def) \ argument
81 DRI_CONF_OPT_BEGIN_V(texture_depth,enum,def,"0:3") \
90 #define DRI_CONF_DEF_MAX_ANISOTROPY(def,range) \ argument
91 DRI_CONF_OPT_BEGIN_V(def_max_anisotropy,float,def,range) \
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