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Searched refs:dmb (Results 1 – 25 of 54) sorted by relevance

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/external/llvm/test/CodeGen/ARM/
Doptimize-dmbs-v7.ll23 ; Hence it should have 3 dmb;str;dmb sequences with the middle dmbs collapsed
26 ; CHECK: dmb
27 ; CHECK-NOT: dmb
31 ; CHECK: dmb
32 ; CHECK-NOT: dmb
36 ; CHECK: dmb
37 ; CHECK-NOT: dmb
41 ; CHECK: dmb
42 ; CHECK-NOT: dmb
48 call void @llvm.arm.dmb(i32 11)
[all …]
Datomic-load-store.ll9 ; ARM: dmb {{ish$}}
11 ; ARM-NEXT: dmb {{ish$}}
15 ; THUMBTWO: dmb {{ish$}}
17 ; THUMBTWO-NEXT: dmb {{ish$}}
25 ; ARM-NEXT: dmb {{ish$}}
30 ; THUMBTWO-NEXT: dmb {{ish$}}
37 ; ARM-NOT: dmb
39 ; ARM-NOT: dmb
41 ; ARM-NOT: dmb
45 ; THUMBTWO-NOT: dmb
[all …]
Dswift-atomics.ll4 ; Release operations only need the store barrier provided by a "dmb ishst",
8 ; CHECK: dmb ishst
11 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
17 ; followed by an acquire does not get reordered. In that case a "dmb ishst" is
21 ; CHECK: dmb ishst
23 ; CHECK: dmb {{ish$}}
25 ; CHECK: dmb {{ish$}}
27 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
28 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
40 ; CHECK: dmb {{ish$}}
[all …]
Datomic-64bit.ll8 ; CHECK: dmb {{ish$}}
17 ; CHECK: dmb {{ish$}}
20 ; CHECK-THUMB: dmb {{ish$}}
29 ; CHECK-THUMB: dmb {{ish$}}
37 ; CHECK: dmb {{ish$}}
46 ; CHECK: dmb {{ish$}}
49 ; CHECK-THUMB: dmb {{ish$}}
58 ; CHECK-THUMB: dmb {{ish$}}
66 ; CHECK: dmb {{ish$}}
75 ; CHECK: dmb {{ish$}}
[all …]
Datomic-ops-v8.ll14 ; CHECK-NOT: dmb
27 ; CHECK-NOT: dmb
37 ; CHECK-NOT: dmb
50 ; CHECK-NOT: dmb
60 ; CHECK-NOT: dmb
73 ; CHECK-NOT: dmb
83 ; CHECK-NOT: dmb
99 ; CHECK-NOT: dmb
110 ; CHECK-NOT: dmb
123 ; CHECK-NOT: dmb
[all …]
Dintrinsics-v8.ll4 ; CHECK: dmb sy
5 call void @llvm.arm.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.arm.dmb(i32 3)
17 declare void @llvm.arm.dmb(i32)
Dcmpxchg-idioms.ll6 ; CHECK: dmb ishst
19 ; CHECK: dmb ish
25 ; CHECK: dmb ish
38 ; CHECK: dmb ishst
70 ; CHECK: dmb ishst
82 ; CHECK: dmb ish
87 ; CHECK: dmb ish
Dintrinsics-memory-barrier.ll6 call void @llvm.arm.dmb(i32 3) ; CHECK: dmb osh
19 call void @llvm.arm.dmb(i32 15) ; CHECK: dmb sy
53 declare void @llvm.arm.dmb(i32)
Dcmpxchg-weak.ll8 ; CHECK: dmb ish
14 ; CHECK: dmb ish
30 ; CHECK: dmb ish
37 ; CHECK: dmb ish
Datomic-op.ll203 ; CHECK: dmb ish
211 ; CHECK: dmb ish
222 ; CHECK-NOT: dmb ish
231 ; CHECK: dmb ish
/external/llvm/test/CodeGen/AArch64/
Datomic-ops.ll18 ; CHECK-NOT: dmb
29 ; CHECK-NOT: dmb
38 ; CHECK-NOT: dmb
49 ; CHECK-NOT: dmb
58 ; CHECK-NOT: dmb
69 ; CHECK-NOT: dmb
78 ; CHECK-NOT: dmb
89 ; CHECK-NOT: dmb
98 ; CHECK-NOT: dmb
109 ; CHECK-NOT: dmb
[all …]
Datomic-ops-not-barriers.ll16 ; CHECK: dmb
18 ; CHECK: dmb
19 ; The key point here is that the second dmb isn't immediately followed by the
Darm64-atomic-128.ll177 ; CHECK-NOT: dmb
179 ; CHECK-NOT: dmb
186 ; CHECK-NOT: dmb
188 ; CHECK-NOT: dmb
196 ; CHECK-NOT: dmb
201 ; CHECK-NOT: dmb
208 ; CHECK-NOT: dmb
213 ; CHECK-NOT: dmb
220 ; CHECK-NOT: dmb
225 ; CHECK-NOT: dmb
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions-v8.s22 dmb ishld
23 dmb oshld
24 dmb nshld
25 dmb ld
27 @ CHECK-V8: dmb ishld @ encoding: [0x59,0xf0,0x7f,0xf5]
28 @ CHECK-V8: dmb oshld @ encoding: [0x51,0xf0,0x7f,0xf5]
29 @ CHECK-V8: dmb nshld @ encoding: [0x55,0xf0,0x7f,0xf5]
30 @ CHECK-V8: dmb ld @ encoding: [0x5d,0xf0,0x7f,0xf5]
Dbasic-thumb2-instructions-v8.s41 dmb ishld
42 dmb oshld
43 dmb nshld
44 dmb ld
46 @ CHECK-V8: dmb ishld @ encoding: [0xbf,0xf3,0x59,0x8f]
47 @ CHECK-V8: dmb oshld @ encoding: [0xbf,0xf3,0x51,0x8f]
48 @ CHECK-V8: dmb nshld @ encoding: [0xbf,0xf3,0x55,0x8f]
49 @ CHECK-V8: dmb ld @ encoding: [0xbf,0xf3,0x5d,0x8f]
Dthumb-hints.s22 dmb sy
23 dmb
28 @ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
29 @ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
49 @ CHECK-ERROR-NEXT: dmb sy
52 @ CHECK-ERROR-NEXT: dmb
Dinvalid-barrier.s7 dmb #0x10
8 dmb imaginary_scope
Dbasic-arm-instructions.s594 dmb #0xf
595 dmb #0xe
596 dmb #0xd
597 dmb #0xc
598 dmb #0xb
599 dmb #0xa
600 dmb #0x9
601 dmb #0x8
602 dmb #0x7
603 dmb #0x6
[all …]
Dbasic-thumb2-instructions.s469 dmb #0xf
470 dmb #0xe
471 dmb #0xd
472 dmb #0xc
473 dmb #0xb
474 dmb #0xa
475 dmb #0x9
476 dmb #0x8
477 dmb #0x7
478 dmb #0x6
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dthumb-v8.txt25 # CHECK: dmb ishld
26 # CHECK: dmb oshld
27 # CHECK: dmb nshld
28 # CHECK: dmb ld
Dbasic-arm-instructions-v8.txt17 # CHECK: dmb ishld
18 # CHECK: dmb oshld
19 # CHECK: dmb nshld
20 # CHECK: dmb ld
/external/compiler-rt/lib/builtins/arm/
Dsync-ops.h22 dmb ; \
29 dmb ; \
37 dmb ; \
44 dmb ; \
/external/llvm/test/MC/AArch64/
Darm64-optional-hash.s20 ; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5]
21 dmb 3 label
/external/llvm/test/CodeGen/Thumb/
D2012-04-26-M0ISelBug.ll2 ; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
Dbarrier.ll10 ; V6M: dmb sy

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