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Searched refs:fcvtau (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s90 fcvtau s12, s13
91 fcvtau d21, d14
Darm64-fp-encoding.s170 fcvtau w1, s2
171 fcvtau w1, d2
172 fcvtau x1, s2
173 fcvtau x1, d2
175 ; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e]
176 ; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e]
177 ; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e]
178 ; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e]
Dneon-simd-misc.s586 fcvtau v6.4s, v8.4s
587 fcvtau v6.2d, v8.2d
588 fcvtau v4.2s, v0.2s
Darm64-advsimd.s641 fcvtau.2s v0, v0
642 fcvtau.4s v0, v0
643 fcvtau.2d v0, v0
644 fcvtau s0, s0
645 fcvtau d0, d0 define
647 ; CHECK: fcvtau.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x2e]
648 ; CHECK: fcvtau.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x6e]
649 ; CHECK: fcvtau.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x6e]
650 ; CHECK: fcvtau s0, s0 ; encoding: [0x00,0xc8,0x21,0x7e]
651 ; CHECK: fcvtau d0, d0 ; encoding: [0x00,0xc8,0x61,0x7e]
Dneon-diagnostics.s5936 fcvtau v0.16b, v31.16b
5937 fcvtau v2.8h, v4.8h
5938 fcvtau v1.8b, v9.8b
5939 fcvtau v13.4h, v21.4h
7192 fcvtau s0, d0
7193 fcvtau d0, s0 define
Dbasic-a64-instructions.s2090 fcvtau w29, s30
2091 fcvtau xzr, s0
2144 fcvtau w29, d30
2145 fcvtau xzr, d0
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll48 ;CHECK: fcvtau w0, s0
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
56 ;CHECK: fcvtau x0, s0
58 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)
64 ;CHECK: fcvtau w0, d0
66 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A)
72 ;CHECK: fcvtau x0, d0
74 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %A)
78 declare i32 @llvm.aarch64.neon.fcvtau.i32.f32(float) nounwind readnone
79 declare i64 @llvm.aarch64.neon.fcvtau.i64.f32(float) nounwind readnone
[all …]
Darm64-vcvt.ll37 ;CHECK: fcvtau.2s v0, v0
39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A)
46 ;CHECK: fcvtau.4s v0, v0
48 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A)
55 ;CHECK: fcvtau.2d v0, v0
57 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)
61 declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone
62 declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone
63 declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone
/external/vixl/doc/
Dchangelog.md23 `frinta`, `fcvtau` and `fcvtas`.
Dsupported-instructions.md1072 ### fcvtau ### subsection
1076 void fcvtau(const Register& rd, const FPRegister& fn)
/external/chromium_org/v8/test/cctest/
Dtest-disasm-arm64.cc1516 COMPARE(fcvtau(w8, s9), "fcvtau w8, s9"); in TEST_()
1517 COMPARE(fcvtau(x10, s11), "fcvtau x10, s11"); in TEST_()
1518 COMPARE(fcvtau(w12, d13), "fcvtau w12, d13"); in TEST_()
1519 COMPARE(fcvtau(x14, d15), "fcvtau x14, d15"); in TEST_()
Dtest-assembler-arm64.cc6927 TEST(fcvtau) { in TEST() argument
/external/vixl/test/
Dtest-disasm-a64.cc1469 COMPARE(fcvtau(w8, s9), "fcvtau w8, s9"); in TEST()
1470 COMPARE(fcvtau(x10, s11), "fcvtau x10, s11"); in TEST()
1471 COMPARE(fcvtau(w12, d13), "fcvtau w12, d13"); in TEST()
1472 COMPARE(fcvtau(x14, d15), "fcvtau x14, d15"); in TEST()
Dtest-simulator-a64.cc1002 DEFINE_TEST_FP_TO_INT(fcvtau, FPToU, Conversions)
Dtest-assembler-a64.cc6130 TEST(fcvtau) { in TEST() argument
/external/vixl/src/a64/
Dmacro-assembler-a64.h571 fcvtau(rd, fn); in Fcvtau()
Dassembler-a64.h1347 void fcvtau(const Register& rd, const FPRegister& fn);
Dassembler-a64.cc1446 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) { in fcvtau() function in vixl::Assembler
/external/chromium_org/v8/src/arm64/
Dmacro-assembler-arm64-inl.h611 fcvtau(rd, fn); in Fcvtau()
Dassembler-arm64.h1691 void fcvtau(const Register& rd, const FPRegister& fn);
Dassembler-arm64.cc2004 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) { in fcvtau() function in v8::internal::Assembler
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1681 # CHECK: fcvtau w29, s30
1682 # CHECK: fcvtau xzr, s0
1735 # CHECK: fcvtau w29, d30
1736 # CHECK: fcvtau xzr, d0
Dneon-instructions.txt2552 # CHECK: fcvtau s12, s13
2553 # CHECK: fcvtau d21, d14
Darm64-advsimd.txt434 # CHECK: fcvtau.2s v0, v0
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2197 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2476 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2975 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;