/external/llvm/test/MC/AArch64/ |
D | neon-scalar-cvt.s | 90 fcvtau s12, s13 91 fcvtau d21, d14
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D | arm64-fp-encoding.s | 170 fcvtau w1, s2 171 fcvtau w1, d2 172 fcvtau x1, s2 173 fcvtau x1, d2 175 ; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e] 176 ; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e] 177 ; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e] 178 ; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e]
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D | neon-simd-misc.s | 586 fcvtau v6.4s, v8.4s 587 fcvtau v6.2d, v8.2d 588 fcvtau v4.2s, v0.2s
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D | arm64-advsimd.s | 641 fcvtau.2s v0, v0 642 fcvtau.4s v0, v0 643 fcvtau.2d v0, v0 644 fcvtau s0, s0 645 fcvtau d0, d0 define 647 ; CHECK: fcvtau.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x2e] 648 ; CHECK: fcvtau.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x6e] 649 ; CHECK: fcvtau.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x6e] 650 ; CHECK: fcvtau s0, s0 ; encoding: [0x00,0xc8,0x21,0x7e] 651 ; CHECK: fcvtau d0, d0 ; encoding: [0x00,0xc8,0x61,0x7e]
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D | neon-diagnostics.s | 5936 fcvtau v0.16b, v31.16b 5937 fcvtau v2.8h, v4.8h 5938 fcvtau v1.8b, v9.8b 5939 fcvtau v13.4h, v21.4h 7192 fcvtau s0, d0 7193 fcvtau d0, s0 define
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D | basic-a64-instructions.s | 2090 fcvtau w29, s30 2091 fcvtau xzr, s0 2144 fcvtau w29, d30 2145 fcvtau xzr, d0
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-cvt.ll | 48 ;CHECK: fcvtau w0, s0 50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A) 56 ;CHECK: fcvtau x0, s0 58 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A) 64 ;CHECK: fcvtau w0, d0 66 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A) 72 ;CHECK: fcvtau x0, d0 74 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %A) 78 declare i32 @llvm.aarch64.neon.fcvtau.i32.f32(float) nounwind readnone 79 declare i64 @llvm.aarch64.neon.fcvtau.i64.f32(float) nounwind readnone [all …]
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D | arm64-vcvt.ll | 37 ;CHECK: fcvtau.2s v0, v0 39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A) 46 ;CHECK: fcvtau.4s v0, v0 48 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A) 55 ;CHECK: fcvtau.2d v0, v0 57 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A) 61 declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone 62 declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone 63 declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone
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/external/vixl/doc/ |
D | changelog.md | 23 `frinta`, `fcvtau` and `fcvtas`.
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D | supported-instructions.md | 1072 ### fcvtau ### subsection 1076 void fcvtau(const Register& rd, const FPRegister& fn)
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/external/chromium_org/v8/test/cctest/ |
D | test-disasm-arm64.cc | 1516 COMPARE(fcvtau(w8, s9), "fcvtau w8, s9"); in TEST_() 1517 COMPARE(fcvtau(x10, s11), "fcvtau x10, s11"); in TEST_() 1518 COMPARE(fcvtau(w12, d13), "fcvtau w12, d13"); in TEST_() 1519 COMPARE(fcvtau(x14, d15), "fcvtau x14, d15"); in TEST_()
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D | test-assembler-arm64.cc | 6927 TEST(fcvtau) { in TEST() argument
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/external/vixl/test/ |
D | test-disasm-a64.cc | 1469 COMPARE(fcvtau(w8, s9), "fcvtau w8, s9"); in TEST() 1470 COMPARE(fcvtau(x10, s11), "fcvtau x10, s11"); in TEST() 1471 COMPARE(fcvtau(w12, d13), "fcvtau w12, d13"); in TEST() 1472 COMPARE(fcvtau(x14, d15), "fcvtau x14, d15"); in TEST()
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D | test-simulator-a64.cc | 1002 DEFINE_TEST_FP_TO_INT(fcvtau, FPToU, Conversions)
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D | test-assembler-a64.cc | 6130 TEST(fcvtau) { in TEST() argument
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/external/vixl/src/a64/ |
D | macro-assembler-a64.h | 571 fcvtau(rd, fn); in Fcvtau()
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D | assembler-a64.h | 1347 void fcvtau(const Register& rd, const FPRegister& fn);
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D | assembler-a64.cc | 1446 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) { in fcvtau() function in vixl::Assembler
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/external/chromium_org/v8/src/arm64/ |
D | macro-assembler-arm64-inl.h | 611 fcvtau(rd, fn); in Fcvtau()
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D | assembler-arm64.h | 1691 void fcvtau(const Register& rd, const FPRegister& fn);
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D | assembler-arm64.cc | 2004 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) { in fcvtau() function in v8::internal::Assembler
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | basic-a64-instructions.txt | 1681 # CHECK: fcvtau w29, s30 1682 # CHECK: fcvtau xzr, s0 1735 # CHECK: fcvtau w29, d30 1736 # CHECK: fcvtau xzr, d0
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D | neon-instructions.txt | 2552 # CHECK: fcvtau s12, s13 2553 # CHECK: fcvtau d21, d14
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D | arm64-advsimd.txt | 434 # CHECK: fcvtau.2s v0, v0
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 2197 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>; 2476 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>; 2975 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
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