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Searched refs:fcvtmu (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s112 fcvtmu s12, s13
113 fcvtmu d21, d14
Darm64-fp-encoding.s190 fcvtmu w1, s2
191 fcvtmu w1, d2
192 fcvtmu x1, s2
193 fcvtmu x1, d2
195 ; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e]
196 ; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e]
197 ; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e]
198 ; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e]
Dneon-simd-misc.s553 fcvtmu v6.4s, v8.4s
554 fcvtmu v6.2d, v8.2d
555 fcvtmu v4.2s, v0.2s
Darm64-advsimd.s675 fcvtmu.2s v0, v0
676 fcvtmu.4s v0, v0
677 fcvtmu.2d v0, v0
678 fcvtmu s0, s0
679 fcvtmu d0, d0 define
681 ; CHECK: fcvtmu.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x2e]
682 ; CHECK: fcvtmu.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x6e]
683 ; CHECK: fcvtmu.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x6e]
684 ; CHECK: fcvtmu s0, s0 ; encoding: [0x00,0xb8,0x21,0x7e]
685 ; CHECK: fcvtmu d0, d0 ; encoding: [0x00,0xb8,0x61,0x7e]
Dneon-diagnostics.s5916 fcvtmu v0.16b, v31.16b
5917 fcvtmu v2.8h, v4.8h
5918 fcvtmu v1.8b, v9.8b
5919 fcvtmu v13.4h, v21.4h
7222 fcvtmu s0, d0
7223 fcvtmu d0, s0 define
Dbasic-a64-instructions.s2063 fcvtmu w6, s7
2064 fcvtmu x8, s9
2117 fcvtmu w6, d7
2118 fcvtmu x8, d9
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll128 ;CHECK: fcvtmu w0, s0
130 %tmp3 = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float %A)
136 ;CHECK: fcvtmu x0, s0
138 %tmp3 = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float %A)
144 ;CHECK: fcvtmu w0, d0
146 %tmp3 = call i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double %A)
152 ;CHECK: fcvtmu x0, d0
154 %tmp3 = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %A)
158 declare i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float) nounwind readnone
159 declare i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float) nounwind readnone
[all …]
Darm64-vcvt.ll99 ;CHECK: fcvtmu.2s v0, v0
101 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> %A)
108 ;CHECK: fcvtmu.4s v0, v0
110 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> %A)
117 ;CHECK: fcvtmu.2d v0, v0
119 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A)
123 declare <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone
124 declare <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone
125 declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone
/external/chromium_org/v8/test/cctest/
Dtest-disasm-arm64.cc1562 COMPARE(fcvtmu(w8, s9), "fcvtmu w8, s9"); in TEST_()
1563 COMPARE(fcvtmu(x10, s11), "fcvtmu x10, s11"); in TEST_()
1564 COMPARE(fcvtmu(w12, d13), "fcvtmu w12, d13"); in TEST_()
1565 COMPARE(fcvtmu(x14, d15), "fcvtmu x14, d15"); in TEST_()
Dtest-assembler-arm64.cc7132 TEST(fcvtmu) { in TEST() argument
/external/vixl/test/
Dtest-disasm-a64.cc1515 COMPARE(fcvtmu(w8, s9), "fcvtmu w8, s9"); in TEST()
1516 COMPARE(fcvtmu(x10, s11), "fcvtmu x10, s11"); in TEST()
1517 COMPARE(fcvtmu(w12, d13), "fcvtmu w12, d13"); in TEST()
1518 COMPARE(fcvtmu(x14, d15), "fcvtmu x14, d15"); in TEST()
Dtest-simulator-a64.cc1004 DEFINE_TEST_FP_TO_INT(fcvtmu, FPToU, Conversions)
Dtest-assembler-a64.cc6333 TEST(fcvtmu) { in TEST() argument
/external/vixl/doc/
Dsupported-instructions.md1086 ### fcvtmu ### subsection
1090 void fcvtmu(const Register& rd, const FPRegister& fn)
/external/vixl/src/a64/
Dmacro-assembler-a64.h581 fcvtmu(rd, fn); in Fcvtmu()
Dassembler-a64.h1353 void fcvtmu(const Register& rd, const FPRegister& fn);
Dassembler-a64.cc1456 void Assembler::fcvtmu(const Register& rd, const FPRegister& fn) { in fcvtmu() function in vixl::Assembler
/external/chromium_org/v8/src/arm64/
Dmacro-assembler-arm64-inl.h625 fcvtmu(rd, fn); in Fcvtmu()
Dassembler-arm64.h1697 void fcvtmu(const Register& rd, const FPRegister& fn);
Dassembler-arm64.cc2014 void Assembler::fcvtmu(const Register& rd, const FPRegister& fn) { in fcvtmu() function in v8::internal::Assembler
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1654 # CHECK: fcvtmu w6, s7
1655 # CHECK: fcvtmu x8, s9
1708 # CHECK: fcvtmu w6, d7
1709 # CHECK: fcvtmu x8, d9
Dneon-instructions.txt2570 # CHECK: fcvtmu s12, s13
2571 # CHECK: fcvtmu d21, d14
Darm64-advsimd.txt436 # CHECK: fcvtmu.2s v0, v0
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2199 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2489 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2977 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;