/external/llvm/test/MC/AArch64/ |
D | neon-scalar-cvt.s | 134 fcvtnu s12, s13 135 fcvtnu d21, d14
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D | arm64-fp-encoding.s | 210 fcvtnu w1, s2 211 fcvtnu w1, d2 212 fcvtnu x1, s2 213 fcvtnu x1, d2 215 ; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e] 216 ; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e] 217 ; CHECK: fcvtnu x1, s2 ; encoding: [0x41,0x00,0x21,0x9e] 218 ; CHECK: fcvtnu x1, d2 ; encoding: [0x41,0x00,0x61,0x9e]
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D | neon-simd-misc.s | 521 fcvtnu v6.4s, v8.4s 522 fcvtnu v6.2d, v8.2d 523 fcvtnu v4.2s, v0.2s
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D | arm64-advsimd.s | 699 fcvtnu.2s v0, v0 700 fcvtnu.4s v0, v0 701 fcvtnu.2d v0, v0 702 fcvtnu s0, s0 703 fcvtnu d0, d0 define 705 ; CHECK: fcvtnu.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x2e] 706 ; CHECK: fcvtnu.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x6e] 707 ; CHECK: fcvtnu.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x6e] 708 ; CHECK: fcvtnu s0, s0 ; encoding: [0x00,0xa8,0x21,0x7e] 709 ; CHECK: fcvtnu d0, d0 ; encoding: [0x00,0xa8,0x61,0x7e]
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D | neon-diagnostics.s | 5896 fcvtnu v0.16b, v31.16b 5897 fcvtnu v2.8h, v4.8h 5898 fcvtnu v1.8b, v9.8b 5899 fcvtnu v13.4h, v21.4h 7252 fcvtnu s0, d0 7253 fcvtnu d0, s0 define
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D | basic-a64-instructions.s | 2045 fcvtnu wzr, s12 2046 fcvtnu x0, s0 2099 fcvtnu wzr, d12 2100 fcvtnu x0, d0
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-cvt.ll | 208 ;CHECK: fcvtnu w0, s0 210 %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %A) 216 ;CHECK: fcvtnu x0, s0 218 %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float %A) 224 ;CHECK: fcvtnu w0, d0 226 %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double %A) 232 ;CHECK: fcvtnu x0, d0 234 %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %A) 238 declare i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float) nounwind readnone 239 declare i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float) nounwind readnone [all …]
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D | arm64-vcvt.ll | 223 ;CHECK: fcvtnu.2s v0, v0 225 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A) 232 ;CHECK: fcvtnu.4s v0, v0 234 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A) 241 ;CHECK: fcvtnu.2d v0, v0 243 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A) 247 declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone 248 declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone 249 declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind readnone
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/external/chromium_org/v8/test/cctest/ |
D | test-disasm-arm64.cc | 1524 COMPARE(fcvtnu(w8, s9), "fcvtnu w8, s9"); in TEST_() 1525 COMPARE(fcvtnu(x10, s11), "fcvtnu x10, s11"); in TEST_() 1526 COMPARE(fcvtnu(w12, d13), "fcvtnu w12, d13"); in TEST_() 1527 COMPARE(fcvtnu(x14, d15), "fcvtnu x14, d15"); in TEST_()
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D | test-assembler-arm64.cc | 7340 TEST(fcvtnu) { in TEST() argument
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/external/vixl/test/ |
D | test-disasm-a64.cc | 1477 COMPARE(fcvtnu(w8, s9), "fcvtnu w8, s9"); in TEST() 1478 COMPARE(fcvtnu(x10, s11), "fcvtnu x10, s11"); in TEST() 1479 COMPARE(fcvtnu(w12, d13), "fcvtnu w12, d13"); in TEST() 1480 COMPARE(fcvtnu(x14, d15), "fcvtnu x14, d15"); in TEST()
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D | test-simulator-a64.cc | 1006 DEFINE_TEST_FP_TO_INT(fcvtnu, FPToU, Conversions)
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D | test-assembler-a64.cc | 6539 TEST(fcvtnu) { in TEST() argument
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/external/vixl/doc/ |
D | supported-instructions.md | 1100 ### fcvtnu ### subsection 1104 void fcvtnu(const Register& rd, const FPRegister& fn)
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/external/vixl/src/a64/ |
D | macro-assembler-a64.h | 591 fcvtnu(rd, fn); in Fcvtnu()
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D | assembler-a64.h | 1359 void fcvtnu(const Register& rd, const FPRegister& fn);
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D | assembler-a64.cc | 1466 void Assembler::fcvtnu(const Register& rd, const FPRegister& fn) { in fcvtnu() function in vixl::Assembler
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-advsimd.txt | 438 # CHECK: fcvtnu.2s v0, v0 550 # 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0" 567 # "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0"
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D | basic-a64-instructions.txt | 1636 # CHECK: fcvtnu wzr, s12 1637 # CHECK: fcvtnu x0, s0 1690 # CHECK: fcvtnu wzr, d12 1691 # CHECK: fcvtnu x0, d0
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D | neon-instructions.txt | 2591 # CHECK: fcvtnu s12, s13 2592 # CHECK: fcvtnu d21, d14
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/external/chromium_org/v8/src/arm64/ |
D | macro-assembler-arm64-inl.h | 639 fcvtnu(rd, fn); in Fcvtnu()
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D | assembler-arm64.h | 1703 void fcvtnu(const Register& rd, const FPRegister& fn);
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D | assembler-arm64.cc | 2024 void Assembler::fcvtnu(const Register& rd, const FPRegister& fn) { in fcvtnu() function in v8::internal::Assembler
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 2201 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>; 2491 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>; 2979 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
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