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Searched refs:fcvtzu (Results 1 – 25 of 34) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s59 fcvtzu s21, s12, #1
60 fcvtzu d21, d12, #1
177 fcvtzu s12, s13
178 fcvtzu d21, d14
Darm64-fp-encoding.s258 fcvtzu w1, s2
259 fcvtzu w1, s2, #1
260 fcvtzu w1, d2
261 fcvtzu w1, d2, #1
262 fcvtzu x1, s2
263 fcvtzu x1, s2, #1
264 fcvtzu x1, d2
265 fcvtzu x1, d2, #1
267 ; CHECK: fcvtzu w1, s2 ; encoding: [0x41,0x00,0x39,0x1e]
268 ; CHECK: fcvtzu w1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x1e]
[all …]
Dneon-simd-shift.s423 fcvtzu v0.2s, v1.2s, #3
424 fcvtzu v0.4s, v1.4s, #3
425 fcvtzu v0.2d, v1.2d, #3
Dneon-simd-misc.s570 fcvtzu v6.4s, v8.4s
571 fcvtzu v6.2d, v8.2d
572 fcvtzu v4.2s, v0.2s
Dbasic-a64-instructions.s1956 fcvtzu w3, s5, #1
1957 fcvtzu wzr, s20, #13
1958 fcvtzu w19, s0, #32
1963 fcvtzu x3, s5, #1
1964 fcvtzu x12, s30, #45
1965 fcvtzu x19, s0, #64
1970 fcvtzu w3, d5, #1
1971 fcvtzu wzr, d20, #13
1972 fcvtzu w19, d0, #32
1977 fcvtzu x3, d5, #1
[all …]
Darm64-advsimd.s761 fcvtzu.2s v0, v0
762 fcvtzu.4s v0, v0
763 fcvtzu.2d v0, v0
764 fcvtzu s0, s0
765 fcvtzu d0, d0 define
767 ; CHECK: fcvtzu.2s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x2e]
768 ; CHECK: fcvtzu.4s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x6e]
769 ; CHECK: fcvtzu.2d v0, v0 ; encoding: [0x00,0xb8,0xe1,0x6e]
770 ; CHECK: fcvtzu s0, s0 ; encoding: [0x00,0xb8,0xa1,0x7e]
771 ; CHECK: fcvtzu d0, d0 ; encoding: [0x00,0xb8,0xe1,0x7e]
[all …]
Dbasic-a64-diagnostics.s1678 fcvtzu w13, s31, #0
1679 fcvtzu w19, s20, #33
1680 fcvtzu wsp, s19, #14
1691 fcvtzu x13, s31, #0
1692 fcvtzu x19, s20, #65
1693 fcvtzu sp, s19, #14
Dneon-diagnostics.s2071 fcvtzu v0.2s, v1.2s, #33
2072 fcvtzu v0.4s, v1.4s, #33
2073 fcvtzu v0.2d, v1.2d, #65
5926 fcvtzu v0.16b, v31.16b
5927 fcvtzu v2.8h, v4.8h
5928 fcvtzu v1.8b, v9.8b
5929 fcvtzu v13.4h, v21.4h
6295 fcvtzu s21, s12, #33
6296 fcvtzu d21, d12, #0
6297 fcvtzu s21, d12, #1
[all …]
/external/llvm/test/CodeGen/AArch64/
Dfcvt-fixed.ll61 ; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #7
66 ; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #32
71 ; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #7
76 ; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #64
81 ; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #7
86 ; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #32
91 ; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #7
96 ; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #64
Darm64-2012-06-06-FPToUI.ll11 ; CHECK: fcvtzu x{{[0-9]+}}, d{{[0-9]+}}
12 ; CHECK: fcvtzu w{{[0-9]+}}, d{{[0-9]+}}
31 ; CHECK: fcvtzu x{{[0-9]+}}, s{{[0-9]+}}
32 ; CHECK: fcvtzu w{{[0-9]+}}, s{{[0-9]+}}
Darm64-cvt.ll368 ;CHECK: fcvtzu w0, s0
370 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %A)
376 ;CHECK: fcvtzu x0, s0
378 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float %A)
384 ;CHECK: fcvtzu w0, d0
386 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double %A)
392 ;CHECK: fcvtzu x0, d0
394 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %A)
398 declare i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float) nounwind readnone
399 declare i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float) nounwind readnone
[all …]
Dfcvt-int.ll8 ; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}}
23 ; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}}
38 ; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}}
53 ; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}}
Darm64-vcvt_su32_f32.ll13 ; CHECK: fcvtzu.2s v0, v0
29 ; CHECK: fcvtzu.4s v0, v0
Dcomplex-fp-to-int.ll15 ; CHECK: fcvtzu.2d v0, [[VAL64]]
64 ; CHECK: fcvtzu.4s [[VAL64:v[0-9]+]], v0
100 ; CHECK: fcvtzu.2d [[VAL64:v[0-9]+]], v0
Darm64-fast-isel-noconvert.ll24 ; CHECK: fcvtzu.2s v0, v0
Darm64-vcvt.ll282 ;CHECK: fcvtzu.2s v0, v0
291 ;CHECK: fcvtzu.4s v0, v0
300 ;CHECK: fcvtzu.2d v0, v0
578 ;CHECK: fcvtzu.2s v0, v0, #1
587 ;CHECK: fcvtzu.4s v0, v0, #1
596 ;CHECK: fcvtzu.2d v0, v0, #1
Darm64-fast-isel-conversion.ll228 ; CHECK: fcvtzu w0, s0
237 ; CHECK: fcvtzu w0, d0
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1547 # CHECK: fcvtzu w3, s5, #1
1548 # CHECK: fcvtzu wzr, s20, #13
1549 # CHECK: fcvtzu w19, s0, #32
1554 # CHECK: fcvtzu x3, s5, #1
1555 # CHECK: fcvtzu x12, s30, #45
1556 # CHECK: fcvtzu x19, s0, #64
1561 # CHECK: fcvtzu w3, d5, #1
1562 # CHECK: fcvtzu wzr, d20, #13
1563 # CHECK: fcvtzu w19, d0, #32
1568 # CHECK: fcvtzu x3, d5, #1
[all …]
Dneon-instructions.txt1102 # CHECK: fcvtzu v0.2s, v1.2s, #3
1103 # CHECK: fcvtzu v0.4s, v1.4s, #3
1104 # CHECK: fcvtzu v0.2d, v1.2d, #3
2002 # CHECK: fcvtzu s21, s12, #1
2003 # CHECK: fcvtzu d21, d12, #1
2626 # CHECK: fcvtzu s12, s13
2627 # CHECK: fcvtzu d21, d14
Darm64-advsimd.txt442 # CHECK: fcvtzu.2s v0, v0
1992 # CHECK: fcvtzu.2s v0, v0, #31
1993 # CHECK: fcvtzu.4s v0, v0, #30
1994 # CHECK: fcvtzu.2d v0, v0, #61
/external/chromium_org/v8/test/cctest/
Dtest-disasm-arm64.cc1528 COMPARE(fcvtzu(x16, d17), "fcvtzu x16, d17"); in TEST_()
1529 COMPARE(fcvtzu(w18, d19), "fcvtzu w18, d19"); in TEST_()
1532 COMPARE(fcvtzu(x16, s17), "fcvtzu x16, s17"); in TEST_()
1533 COMPARE(fcvtzu(w18, s19), "fcvtzu w18, s19"); in TEST_()
/external/vixl/test/
Dtest-disasm-a64.cc1481 COMPARE(fcvtzu(x16, d17), "fcvtzu x16, d17"); in TEST()
1482 COMPARE(fcvtzu(w18, d19), "fcvtzu w18, d19"); in TEST()
1485 COMPARE(fcvtzu(x16, s17), "fcvtzu x16, s17"); in TEST()
1486 COMPARE(fcvtzu(w18, s19), "fcvtzu w18, s19"); in TEST()
Dtest-simulator-a64.cc1008 DEFINE_TEST_FP_TO_INT(fcvtzu, FPToU, Conversions)
/external/vixl/doc/
Dsupported-instructions.md1114 ### fcvtzu ### subsection
1118 void fcvtzu(const Register& rd, const FPRegister& fn)
/external/vixl/src/a64/
Dmacro-assembler-a64.h601 fcvtzu(rd, fn); in Fcvtzu()

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