/external/eigen/Eigen/src/Core/products/ |
D | GeneralBlockPanelKernel.h | 206 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, AccPacket& tmp… 277 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp… 379 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, DoublePacket& c, RhsPacket& … 385 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, ResPacket& c, RhsPacket& /*t… 482 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp… 606 traits.madd(A0,B_0,C0,T0); 607 traits.madd(A1,B_0,C4,B_0); 609 traits.madd(A0,B_0,C1,T0); 610 traits.madd(A1,B_0,C5,B_0); 615 traits.madd(A0,B_0,C0,T0); [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | mul-lohi.ll | 7 ; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]] 8 ; CHECK: madd x1, x1, x2, [[PART1]] 13 ; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]] 14 ; CHECK-BE: madd x0, x0, x3, [[PART1]]
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D | aarch64-fix-cortex-a53-835769.ll | 33 ; CHECK-NEXT: madd 36 ; CHECK-NOWORKAROUND-NEXT: madd 39 ; CHECK-BASIC-PASS-DISABLED-NEXT: madd 51 ; CHECK-NEXT: madd 54 ; CHECK-NOWORKAROUND-NEXT: madd 312 ; CHECK-NEXT: madd 315 ; CHECK-NOWORKAROUND-NEXT: madd 328 ; CHECK-NEXT: madd 331 ; CHECK-NOWORKAROUND-NEXT: madd 409 ; CHECK-NEXT: madd [all …]
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D | dp-3source.ll | 7 ; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 15 ; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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/external/llvm/test/MC/Mips/ |
D | micromips-multiply-instructions.s | 12 # CHECK-EL: madd $4, $5 # encoding: [0xa4,0x00,0x3c,0xcb] 19 # CHECK-EB: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c] 23 madd $4, $5
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D | mips-dsp-instructions.s | 31 # CHECK: madd $ac1, $6, $7 # encoding: [0x70,0xc7,0x08,0x00] 42 # CHECK: madd $6, $7 # encoding: [0x70,0xc7,0x00,0x00] 79 madd $ac1, $6, $7 90 madd $6, $7
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D | micromips-fpu-instructions.s | 64 # CHECK-EL: madd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x01,0x11] 65 # CHECK-EL: madd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x09,0x11] 127 # CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01] 128 # CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09] 186 madd.s $f2, $f4, $f6, $f8 187 madd.d $f2, $f4, $f6, $f8
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D | mips64-alu-instructions.s | 78 # CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] 103 madd $6,$7
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D | mips-alu-instructions.s | 82 # CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] 107 madd $6,$7
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/external/llvm/test/MC/Mips/mips32r6/ |
D | invalid-mips32r2.s | 8 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 9 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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D | invalid-mips32.s | 8 …madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature … 9 …madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature …
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/external/llvm/test/CodeGen/Mips/ |
D | inlineasm-cnstrnt-reg.ll | 37 ; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwi…
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D | fmadd1.ll | 1 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported 32 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 47 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 117 ; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 134 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 198 ; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 214 ; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13 285 ; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 303 ; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
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/external/llvm/test/MC/Mips/mips4/ |
D | invalid-mips64r2.s | 18 …madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 19 …madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 20 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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D | invalid-mips64.s | 15 …madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no… 16 …madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
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/external/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64.s | 16 …madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no… 17 …madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
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D | invalid-mips64r2.s | 22 …madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 23 …madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 24 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm/test/MC/Mips/mips32r2/ |
D | valid.s | 76 madd $s6,$13 77 madd $zero,$9 78 madd.d $f18,$f19,$f26,$f20 79 madd.s $f1,$f31,$f19,$f25
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/external/llvm/test/MC/Mips/mips2/ |
D | invalid-mips32r2.s | 21 …madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 22 …madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 23 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 24 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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D | invalid-mips32.s | 17 …madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur… 18 …madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
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/external/llvm/test/CodeGen/Mips/msa/ |
D | 3rf_4rf_q.ll | 17 %3 = tail call <8 x i16> @llvm.mips.madd.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) 22 declare <8 x i16> @llvm.mips.madd.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind 42 %3 = tail call <4 x i32> @llvm.mips.madd.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) 47 declare <4 x i32> @llvm.mips.madd.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
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/external/libvorbis/ |
D | configure.ac | 177 CFLAGS="-O3 -Wall -Wextra -ffast-math -mfused-madd -D_REENTRANT" 178 PROFILE="-pg -g -O3 -ffast-math -mfused-madd -D_REENTRANT";; 181 CFLAGS="-O3 -Wall -Wextra -ffast-math -mfused-madd -mcpu=750 -D_REENTRANT" 182 PROFILE="-pg -g -O3 -ffast-math -mfused-madd -mcpu=750 -D_REENTRANT";;
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/external/clang/test/SemaCXX/ |
D | vector-casts.cpp | 43 void madd(const testvec& rhs) { in madd() function
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/external/llvm/test/MC/Mips/mips32/ |
D | invalid-mips32r2.s | 15 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 16 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm/test/CodeGen/X86/ |
D | commute-intrinsic.ll | 7 define <2 x i64> @madd(<2 x i64> %b) nounwind {
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