/external/llvm/test/CodeGen/AArch64/ |
D | arm64-neon-mul-div.ll | 333 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 341 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 343 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 345 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 347 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 349 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 351 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 353 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 355 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 363 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} [all …]
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D | arm64-fast-isel-rem.ll | 17 ; CHECK: msub w0, [[TMP]], w1, w0 25 ; CHECK: msub x0, [[TMP]], x1, x0 33 ; CHECK: msub w0, [[TMP]], w1, w0 41 ; CHECK: msub x0, [[TMP]], x1, x0
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D | aarch64-fix-cortex-a53-835769.ll | 67 ; CHECK-NEXT: msub 70 ; CHECK-NOWORKAROUND-NEXT: msub 82 ; CHECK-NEXT: msub 85 ; CHECK-NOWORKAROUND-NEXT: msub 345 ; CHECK-NEXT: msub 348 ; CHECK-NOWORKAROUND-NEXT: msub 361 ; CHECK-NEXT: msub 364 ; CHECK-NOWORKAROUND-NEXT: msub 444 ; CHECK-NEXT: msub 447 ; CHECK-NOWORKAROUND-NEXT: msub [all …]
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D | dp-3source.ll | 23 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 31 ; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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/external/chromium_org/v8/src/compiler/ |
D | machine-operator-reducer.cc | 167 Int32BinopMatcher msub(m.left().node()); in Reduce() local 168 node->ReplaceInput(0, msub.left().node()); in Reduce() 169 node->ReplaceInput(1, msub.right().node()); in Reduce() 285 Int32BinopMatcher msub(m.left().node()); in Reduce() local 286 node->ReplaceInput(0, msub.left().node()); in Reduce() 287 node->ReplaceInput(1, msub.right().node()); in Reduce() 291 Int32BinopMatcher msub(m.right().node()); in Reduce() local 292 node->ReplaceInput(0, msub.right().node()); in Reduce() 293 node->ReplaceInput(1, msub.left().node()); in Reduce() 305 Int32BinopMatcher msub(m.left().node()); in Reduce() local [all …]
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/external/llvm/test/MC/Mips/ |
D | micromips-multiply-instructions.s | 14 # CHECK-EL: msub $4, $5 # encoding: [0xa4,0x00,0x3c,0xeb] 21 # CHECK-EB: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c] 25 msub $4, $5
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D | mips-dsp-instructions.s | 33 # CHECK: msub $ac3, $10, $11 # encoding: [0x71,0x4b,0x18,0x04] 44 # CHECK: msub $10, $11 # encoding: [0x71,0x4b,0x00,0x04] 81 msub $ac3, $10, $11 92 msub $10, $11
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D | micromips-fpu-instructions.s | 66 # CHECK-EL: msub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x21,0x11] 67 # CHECK-EL: msub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x29,0x11] 129 # CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21] 130 # CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29] 188 msub.s $f2, $f4, $f6, $f8 189 msub.d $f2, $f4, $f6, $f8
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D | mips64-alu-instructions.s | 80 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70] 105 msub $6,$7
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D | mips-alu-instructions.s | 84 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70] 109 msub $6,$7
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/external/llvm/test/MC/Mips/mips32r6/ |
D | invalid-mips32r2.s | 10 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 11 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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D | invalid-mips32.s | 24 …msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature …
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/external/llvm/test/CodeGen/Mips/ |
D | fmadd1.ll | 1 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported 73 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 88 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 163 ; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 172 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 240 ; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 256 ; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13 332 ; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 350 ; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
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/external/chromium_org/chrome/browser/resources/chromeos/chromevox/walkers/ |
D | math_shifter_test.unitjs | 119 '<msub><mi>x</mi><mn>3</mn></msub>' +
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/external/llvm/test/CodeGen/Mips/msa/ |
D | 3rf_4rf_q.ll | 117 %3 = tail call <8 x i16> @llvm.mips.msub.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) 122 declare <8 x i16> @llvm.mips.msub.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind 142 %3 = tail call <4 x i32> @llvm.mips.msub.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) 147 declare <4 x i32> @llvm.mips.msub.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
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/external/llvm/test/MC/Mips/mips32/ |
D | invalid-mips32r2.s | 18 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 19 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm/test/MC/Mips/mips32r2/ |
D | valid.s | 104 msub $s7,$k1 105 msub.d $f10,$f1,$f31,$f18 106 msub.s $f12,$f19,$f10,$f16
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/external/llvm/test/MC/Mips/mips4/ |
D | invalid-mips64r2.s | 25 …msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 26 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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D | invalid-mips64.s | 20 …msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
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/external/llvm/test/MC/Mips/mips2/ |
D | invalid-mips32r2.s | 46 …msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 47 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 48 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64r2.s | 29 …msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 30 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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D | invalid-mips64.s | 21 …msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
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/external/llvm/lib/Target/Mips/ |
D | MicroMipsInstrFPU.td | 133 def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 142 def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
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/external/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 19 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/chromium_org/third_party/WebKit/Source/core/css/ |
D | mathml.css | 42 …antics > mphantom, semantics > mfenced, semantics > menclose, semantics > msub, semantics > msup, …
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