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/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/
Dvp9_loopfilter_16_neon.asm36 vld1.8 {d0}, [r2] ; load blimit0 to first half q
37 vld1.8 {d2}, [r3] ; load limit0 to first half q
42 vld1.8 {d4}, [r12] ; load thresh0 to first half q
46 vld1.8 {d1}, [r2] ; load blimit1 to 2nd half q
50 vld1.8 {d3}, [r3] ; load limit1 to 2nd half q
51 vld1.8 {d5}, [r12] ; load thresh1 to 2nd half q
Dvp9_idct8x8_add_neon.asm75 ; stage 2 & stage 3 - even half
139 ; stage 3 -odd half
142 ; stage 2 - odd half
391 ; stage 2 & stage 3 - even half
407 ; stage 3 -odd half
415 ; stage 2 - odd half
Dvp9_iht8x8_add_neon.asm174 ; stage 2 & stage 3 - even half
237 ; stage 3 -odd half
240 ; stage 2 - odd half
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/armv6/
Dvp8_variance_halfpixvar16x16_hv_armv6.asm53 ; z = (x + y + 1) >> 1, interpolate half pixel values vertically
96 ; z = (x + y + 1) >> 1, interpolate half pixel values vertically
138 ; z = (x + y + 1) >> 1, interpolate half pixel values vertically
178 ; z = (x + y + 1) >> 1, interpolate half pixel values vertically
Dintra4x4_predict_v6.asm196 add r8, r0, r8, lsl #14 ; (tl + 2*l[0] + l[1])>>2 in top half
197 add r9, r0, r4, lsl #14 ; (l[0] + 2*l[1] + l[2])>>2 in top half
198 add r10,r0, r5, lsl #14 ; (l[1] + 2*l[2] + l[3])>>2 in top half
199 add r11,r0, r6, lsl #14 ; (l[2] + 2*l[3] + l[3])>>2 in top half
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/test/
Dvariance_test.cc153 const int half = block_size_ / 2; in OneQuarterTest() local
154 memset(ref_, 255, half); in OneQuarterTest()
155 memset(ref_ + half, 0, half); in OneQuarterTest()
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/x86/
Dvp9_intrapred_ssse3.asm193 ; first 4 lines and first half of 3rd 4 lines
253 ; write 4x4 lines (and the first half of the second 4x4 lines)
281 ; write second half of second 4x4 lines
918 ; output 1st 8 lines (and half of 2nd 8 lines)
964 ; output 2nd half of 2nd 8 lines and half of 3rd 8 lines
993 ; output 2nd half of 3rd 8 lines and half of 4th 8 lines
1023 ; output last half of 4th 8 lines
/hardware/intel/common/libva/test/basic/
Dtestplan.txt95 - Render single MPEG2 I-frame, copy half of a VAImage to surface, copy
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/
Dsixtappredict4x4_neon.asm80 vswp d7, d8 ;discard 2nd half data after src_ptr[3] is done
144 vswp d7, d8 ;discard 2nd half data after src_ptr[3] is done
292 vswp d7, d8 ;discard 2nd half data after src_ptr[3] is done
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/ppc/
Dfdct_altivec.asm22 ;# in normalization (fwd is twice unitary, inv is half unitary)
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/ppc/
Dvariance_altivec.asm52 ;# can be used. Only have a half word signed
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vpx_scale/arm/neon/
Dvp8_vpxyv12_extendframeborders_neon.asm140 mov r1, r7 ; src_ptr1 needs to be saved for second half of loop
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/
DCHANGELOG295 Improve SSE2 half-pixel filter funtions
368 ARMv6 optimized half pixel variance calculations
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/encoder/x86/
Dvp9_subpel_variance.asm421 ; tables in half for this function, and save 1-2 registers on x86-64.
/hardware/intel/img/libdrm/
Daclocal.m41607 # maximum length that is only half of the actual maximum length, but