Lines Matching refs:lir
688 uint8_t* Arm64Mir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { in EncodeLIRs() argument
690 for (; lir != nullptr; lir = NEXT_LIR(lir)) { in EncodeLIRs()
691 lir->offset = (write_pos - write_buffer); in EncodeLIRs()
692 bool opcode_is_wide = IS_WIDE(lir->opcode); in EncodeLIRs()
693 A64Opcode opcode = UNWIDE(lir->opcode); in EncodeLIRs()
699 if (LIKELY(!lir->flags.is_nop)) { in EncodeLIRs()
708 uint32_t operand = lir->operands[i]; in EncodeLIRs()
785 << " @ 0x" << std::hex << lir->dalvik_offset; in EncodeLIRs()
860 static LIR* GetPrevEmittingLIR(LIR* lir) { in GetPrevEmittingLIR() argument
861 DCHECK(lir != nullptr); in GetPrevEmittingLIR()
862 LIR* prev_lir = lir->prev; in GetPrevEmittingLIR()
872 LIR* lir; in AssembleLIR() local
891 lir = first_fixup_; in AssembleLIR()
893 while (lir != nullptr) { in AssembleLIR()
897 lir->offset += offset_adjustment; in AssembleLIR()
899 lir->flags.generation = generation; in AssembleLIR()
900 switch (static_cast<FixupKind>(lir->flags.fixup)) { in AssembleLIR()
906 LIR *target_lir = lir->target; in AssembleLIR()
908 CodeOffset pc = lir->offset; in AssembleLIR()
910 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment); in AssembleLIR()
916 lir->operands[0] = delta >> 2; in AssembleLIR()
917 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && lir->operands[0] == 1) { in AssembleLIR()
919 offset_adjustment -= lir->flags.size; in AssembleLIR()
920 lir->flags.is_nop = true; in AssembleLIR()
922 lir->flags.fixup = kFixupNone; in AssembleLIR()
930 LIR *target_lir = lir->target; in AssembleLIR()
932 CodeOffset pc = lir->offset; in AssembleLIR()
934 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment); in AssembleLIR()
940 lir->operands[1] = delta >> 2; in AssembleLIR()
944 int16_t opcode = lir->opcode; in AssembleLIR()
945 RegStorage reg(lir->operands[0] | RegStorage::kValid); in AssembleLIR()
946 int32_t imm = lir->operands[1]; in AssembleLIR()
957 lir->opcode = UNWIDE(opcode); in AssembleLIR()
958 lir->operands[0] = As32BitReg(reg).GetReg(); in AssembleLIR()
962 LIR *target_lir = lir->target; in AssembleLIR()
964 CodeOffset pc = lir->offset; in AssembleLIR()
966 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment); in AssembleLIR()
971 DexOffset dalvik_offset = lir->dalvik_offset; in AssembleLIR()
972 LIR* targetLIR = lir->target; in AssembleLIR()
974 offset_adjustment -= lir->flags.size; in AssembleLIR()
975 int32_t encodedImm = EncodeLogicalImmediate(IS_WIDE(opcode), 1 << lir->operands[1]); in AssembleLIR()
977 lir->opcode = IS_WIDE(opcode) ? WIDE(kA64Tst2rl) : kA64Tst2rl; in AssembleLIR()
978 lir->operands[1] = encodedImm; in AssembleLIR()
979 lir->target = nullptr; in AssembleLIR()
980 lir->flags.fixup = EncodingMap[kA64Tst2rl].fixup; in AssembleLIR()
981 lir->flags.size = EncodingMap[kA64Tst2rl].size; in AssembleLIR()
982 offset_adjustment += lir->flags.size; in AssembleLIR()
988 InsertLIRAfter(lir, new_lir); in AssembleLIR()
989 new_lir->offset = lir->offset + lir->flags.size; in AssembleLIR()
995 ReplaceFixup(prev_lir, lir, new_lir); in AssembleLIR()
997 lir = new_lir->u.a.pcrel_next; in AssembleLIR()
1001 lir->operands[2] = delta >> 2; in AssembleLIR()
1005 LIR* target_lir = lir->target; in AssembleLIR()
1008 CodeOffset target_offs = ((target_lir->flags.generation == lir->flags.generation) ? in AssembleLIR()
1010 delta = target_offs - lir->offset; in AssembleLIR()
1011 } else if (lir->operands[2] >= 0) { in AssembleLIR()
1012 const EmbeddedData* tab = UnwrapPointer<EmbeddedData>(lir->operands[2]); in AssembleLIR()
1013 delta = tab->offset + offset_adjustment - lir->offset; in AssembleLIR()
1016 delta = lir->operands[1]; in AssembleLIR()
1021 lir->operands[1] = delta; in AssembleLIR()
1031 if (IS_WIDE(lir->opcode)) { in AssembleLIR()
1032 LIR* prev_insn = GetPrevEmittingLIR(lir); in AssembleLIR()
1040 LIR* new_lir = RawLIR(lir->dalvik_offset, kA64Nop0, 0, 0, 0, 0, 0, nullptr); in AssembleLIR()
1041 new_lir->offset = lir->offset; in AssembleLIR()
1044 InsertLIRBefore(lir, new_lir); in AssembleLIR()
1045 lir->offset += new_lir->flags.size; in AssembleLIR()
1053 LOG(FATAL) << "Unexpected case " << lir->flags.fixup; in AssembleLIR()
1055 prev_lir = lir; in AssembleLIR()
1056 lir = lir->u.a.pcrel_next; in AssembleLIR()
1101 size_t Arm64Mir2Lir::GetInsnSize(LIR* lir) { in GetInsnSize() argument
1102 A64Opcode opcode = UNWIDE(lir->opcode); in GetInsnSize()
1112 for (LIR* lir = head_lir; lir != end_lir; lir = NEXT_LIR(lir)) { in LinkFixupInsns() local
1113 A64Opcode opcode = UNWIDE(lir->opcode); in LinkFixupInsns()
1114 if (!lir->flags.is_nop) { in LinkFixupInsns()
1115 if (lir->flags.fixup != kFixupNone) { in LinkFixupInsns()
1117 lir->flags.size = EncodingMap[opcode].size; in LinkFixupInsns()
1118 lir->flags.fixup = EncodingMap[opcode].fixup; in LinkFixupInsns()
1121 lir->flags.size = 0; in LinkFixupInsns()
1122 lir->flags.fixup = kFixupLabel; in LinkFixupInsns()
1125 lir->flags.use_def_invalid = true; in LinkFixupInsns()
1126 lir->u.a.pcrel_next = nullptr; in LinkFixupInsns()
1128 first_fixup_ = lir; in LinkFixupInsns()
1130 last_fixup->u.a.pcrel_next = lir; in LinkFixupInsns()
1132 last_fixup = lir; in LinkFixupInsns()
1133 lir->offset = offset; in LinkFixupInsns()
1135 offset += lir->flags.size; in LinkFixupInsns()