35 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {  in OpCmpBranch()
40 LIR* Arm64Mir2Lir::OpIT(ConditionCode ccode, const char* guide) {  in OpIT()
46 void Arm64Mir2Lir::OpEndIT(LIR* it) {  in OpEndIT()
57 void Arm64Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,  in GenCmpLong()
71 void Arm64Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,  in GenShiftOpLong()
99 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode,  in GenSelect()
183 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,  in GenSelectConst32()
191 void Arm64Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {  in GenSelect()
223 void Arm64Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {  in GenFusedLongCmpBranch()
268 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value,  in OpCmpImmBranch()
300 LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg,  in OpCmpMemImmBranch()
314 LIR* Arm64Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {  in OpRegCopyNoInsert()
375 void Arm64Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) {  in OpRegCopy()
382 void Arm64Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) {  in OpRegCopyWide()
416 bool Arm64Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div,  in SmallLiteralDivRem()
460 bool Arm64Mir2Lir::SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div,  in SmallLiteralDivRem64()
529 bool Arm64Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div,  in HandleEasyDivRem()
536 bool Arm64Mir2Lir::HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div,  in HandleEasyDivRem64()
602 bool Arm64Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) {  in EasyMultiply()
608 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit,  in GenDivRemLit()
615 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) {  in GenDivRemLit()
629 RegLocation Arm64Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1,  in GenDivRem()
636 RegLocation Arm64Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage r_src1, RegStorage r_src2,  in GenDivRem()
663 bool Arm64Mir2Lir::GenInlinedAbsInt(CallInfo* info) {  in GenInlinedAbsInt()
678 bool Arm64Mir2Lir::GenInlinedAbsLong(CallInfo* info) {  in GenInlinedAbsLong()
693 bool Arm64Mir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) {  in GenInlinedMinMax()
708 bool Arm64Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) {  in GenInlinedPeek()
724 bool Arm64Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) {  in GenInlinedPoke()
740 bool Arm64Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) {  in GenInlinedCas()
826 bool Arm64Mir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) {  in GenInlinedArrayCopyCharArray()
940 void Arm64Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) {  in OpPcRelLoad()
946 bool Arm64Mir2Lir::CanUseOpPcRelDexCacheArrayLoad() const {  in CanUseOpPcRelDexCacheArrayLoad()
950 void Arm64Mir2Lir::OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest,  in OpPcRelDexCacheArrayLoad()
966 LIR* Arm64Mir2Lir::OpVldm(RegStorage r_base, int count) {  in OpVldm()
972 LIR* Arm64Mir2Lir::OpVstm(RegStorage r_base, int count) {  in OpVstm()
978 void Arm64Mir2Lir::GenMaddMsubInt(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,  in GenMaddMsubInt()
989 void Arm64Mir2Lir::GenMaddMsubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,  in GenMaddMsubLong()
1000 void Arm64Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,  in GenMultiplyByTwoBitMultiplier()
1010 void Arm64Mir2Lir::GenDivZeroCheckWide(RegStorage reg ATTRIBUTE_UNUSED) {  in GenDivZeroCheckWide()
1015 LIR* Arm64Mir2Lir::OpTestSuspend(LIR* target) {  in OpTestSuspend()
1025 LIR* Arm64Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) {  in OpDecAndBranch()
1035 bool Arm64Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {  in GenMemBarrier()
1076 void Arm64Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) {  in GenIntToLong()
1085 void Arm64Mir2Lir::GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest,  in GenDivRemLong()
1105 void Arm64Mir2Lir::GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1,  in GenLongOp()
1116 void Arm64Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {  in GenNegLong()
1125 void Arm64Mir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) {  in GenNotLong()
1134 void Arm64Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest,  in GenArithOpLong()
1185 void Arm64Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,  in GenArrayGet()
1259 void Arm64Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,  in GenArrayPut()
1342 void Arm64Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode,  in GenShiftImmOpLong()
1375 void Arm64Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,  in GenArithImmOpLong()
1476 static void SpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {  in SpillCoreRegs()
1495 static void SpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {  in SpillFPRegs()
1514 static int SpillRegsPreSub(Arm64Mir2Lir* m2l, uint32_t core_reg_mask, uint32_t fp_reg_mask,  in SpillRegsPreSub()
1537 static int SpillRegsPreIndexed(Arm64Mir2Lir* m2l, RegStorage base, uint32_t core_reg_mask,  in SpillRegsPreIndexed()
1674 int Arm64Mir2Lir::SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask,  in SpillRegs()
1689 static void UnSpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {  in UnSpillCoreRegs()
1708 static void UnSpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {  in UnSpillFPRegs()
1727 void Arm64Mir2Lir::UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask,  in UnspillRegs()
1783 bool Arm64Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) {  in GenInlinedReverseBits()