Lines Matching refs:is_div

416 bool Arm64Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div,  in SmallLiteralDivRem()  argument
427 if (!is_div) { in SmallLiteralDivRem()
460 bool Arm64Mir2Lir::SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div, in SmallLiteralDivRem64() argument
471 if (!is_div) { in SmallLiteralDivRem64()
529 bool Arm64Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, in HandleEasyDivRem() argument
531 return HandleEasyDivRem64(dalvik_opcode, is_div, rl_src, rl_dest, static_cast<int>(lit)); in HandleEasyDivRem()
536 bool Arm64Mir2Lir::HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div, in HandleEasyDivRem64() argument
546 return SmallLiteralDivRem64(dalvik_opcode, is_div, rl_src, rl_dest, lit); in HandleEasyDivRem64()
548 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, static_cast<int32_t>(lit)); in HandleEasyDivRem64()
570 if (is_div) { in HandleEasyDivRem64()
609 bool is_div) { in GenDivRemLit() argument
610 UNUSED(rl_dest, rl_src1, lit, is_div); in GenDivRemLit()
615 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { in GenDivRemLit() argument
623 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div); in GenDivRemLit()
630 RegLocation rl_src2, bool is_div, int flags) { in GenDivRem() argument
631 UNUSED(rl_dest, rl_src1, rl_src2, is_div, flags); in GenDivRem()
637 bool is_div) { in GenDivRem() argument
641 if (is_div) { in GenDivRem()
1086 RegLocation rl_src1, RegLocation rl_src2, bool is_div, int flags) { in GenDivRemLong() argument
1090 if (HandleEasyDivRem64(opcode, is_div, rl_src1, rl_dest, lit)) { in GenDivRemLong()
1101 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, is_div); in GenDivRemLong()