Lines Matching refs:right_op
113 RegStorage right_op = RegStorage::InvalidReg(); // The operands. in GenSelect() local
126 right_op = zero_reg; in GenSelect()
129 right_op = zero_reg; in GenSelect()
132 right_op = left_op; in GenSelect()
135 right_op = left_op; in GenSelect()
138 right_op = left_op; in GenSelect()
142 right_op = rs_dest; in GenSelect()
164 right_op = t_reg2; in GenSelect()
170 if (!right_op.Valid()) { in GenSelect()
172 right_op = t_reg2; in GenSelect()
178 DCHECK(left_op.Valid() && right_op.Valid()); in GenSelect()
179 NewLIR4(is_wide ? WIDE(opcode) : opcode, rs_dest.GetReg(), left_op.GetReg(), right_op.GetReg(), in GenSelect()
183 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32() argument
187 OpRegReg(kOpCmp, left_op, right_op); in GenSelectConst32()