57 void Arm64Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,  in GenCmpLong()  argument
60   rl_src1 = LoadValueWide(rl_src1, kCoreReg);  in GenCmpLong()
64   OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);  in GenCmpLong()
72                              RegLocation rl_src1, RegLocation rl_shift) {  in GenShiftOpLong()  argument
91   rl_src1 = LoadValueWide(rl_src1, kCoreReg);  in GenShiftOpLong()
93   OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg));  in GenShiftOpLong()
224   RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0);  in GenFusedLongCmpBranch()  local
230   if (rl_src1.is_const) {  in GenFusedLongCmpBranch()
231     std::swap(rl_src1, rl_src2);  in GenFusedLongCmpBranch()
235   rl_src1 = LoadValueWide(rl_src1, kCoreReg);  in GenFusedLongCmpBranch()
243       OpCmpImmBranch(ccode, rl_src1.reg, 0, taken);  in GenFusedLongCmpBranch()
244       OpCmpImmBranch(NegateComparison(ccode), rl_src1.reg, 0, not_taken);  in GenFusedLongCmpBranch()
251       OpRegImm64(kOpCmp, rl_src1.reg, val);  in GenFusedLongCmpBranch()
259   OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);  in GenFusedLongCmpBranch()
608 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit,  in GenDivRemLit()  argument
610   UNUSED(rl_dest, rl_src1, lit, is_div);  in GenDivRemLit()
629 RegLocation Arm64Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1,  in GenDivRem()  argument
631   UNUSED(rl_dest, rl_src1, rl_src2, is_div, flags);  in GenDivRem()
695   RegLocation rl_src1 = info->args[0];  in GenInlinedMinMax()  local
697   rl_src1 = (is_long) ? LoadValueWide(rl_src1, kCoreReg) : LoadValue(rl_src1, kCoreReg);  in GenInlinedMinMax()
701   OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);  in GenInlinedMinMax()
703           rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), (is_min) ? kArmCondLt : kArmCondGt);  in GenInlinedMinMax()
978 void Arm64Mir2Lir::GenMaddMsubInt(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,  in GenMaddMsubInt()  argument
980   rl_src1 = LoadValue(rl_src1, kCoreReg);  in GenMaddMsubInt()
984   NewLIR4(is_sub ? kA64Msub4rrrr : kA64Madd4rrrr, rl_result.reg.GetReg(), rl_src1.reg.GetReg(),  in GenMaddMsubInt()
989 void Arm64Mir2Lir::GenMaddMsubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,  in GenMaddMsubLong()  argument
991   rl_src1 = LoadValueWide(rl_src1, kCoreReg);  in GenMaddMsubLong()
996           rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), rl_src3.reg.GetReg());  in GenMaddMsubLong()
1086                                  RegLocation rl_src1, RegLocation rl_src2, bool is_div, int flags) {  in GenDivRemLong()  argument
1090     if (HandleEasyDivRem64(opcode, is_div, rl_src1, rl_dest, lit)) {  in GenDivRemLong()
1096   rl_src1 = LoadValueWide(rl_src1, kCoreReg);  in GenDivRemLong()
1101   rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, is_div);  in GenDivRemLong()
1105 void Arm64Mir2Lir::GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1,  in GenLongOp()  argument
1109   rl_src1 = LoadValueWide(rl_src1, kCoreReg);  in GenLongOp()
1112   OpRegRegRegShift(op, rl_result.reg, rl_src1.reg, rl_src2.reg, ENCODE_NO_SHIFT);  in GenLongOp()
1135                                   RegLocation rl_src1, RegLocation rl_src2, int flags) {  in GenArithOpLong()  argument
1142       GenLongOp(kOpAdd, rl_dest, rl_src1, rl_src2);  in GenArithOpLong()
1146       GenLongOp(kOpSub, rl_dest, rl_src1, rl_src2);  in GenArithOpLong()
1150       GenLongOp(kOpMul, rl_dest, rl_src1, rl_src2);  in GenArithOpLong()
1154       GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true, flags);  in GenArithOpLong()
1158       GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false, flags);  in GenArithOpLong()
1162       GenLongOp(kOpAnd, rl_dest, rl_src1, rl_src2);  in GenArithOpLong()
1166       GenLongOp(kOpOr, rl_dest, rl_src1, rl_src2);  in GenArithOpLong()
1170       GenLongOp(kOpXor, rl_dest, rl_src1, rl_src2);  in GenArithOpLong()
1376                                      RegLocation rl_src1, RegLocation rl_src2, int flags) {  in GenArithImmOpLong()  argument
1405       return GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags);  in GenArithImmOpLong()
1410       DCHECK(rl_src1.is_const);  in GenArithImmOpLong()
1411       std::swap(rl_src1, rl_src2);  in GenArithImmOpLong()
1417   rl_src1 = LoadValueWide(rl_src1, kCoreReg);  in GenArithImmOpLong()
1419   OpRegRegImm64(op, rl_result.reg, rl_src1.reg, val);  in GenArithImmOpLong()