87 RegLocation Arm64Mir2Lir::LocCReturn() {  in LocCReturn()
91 RegLocation Arm64Mir2Lir::LocCReturnRef() {  in LocCReturnRef()
95 RegLocation Arm64Mir2Lir::LocCReturnWide() {  in LocCReturnWide()
99 RegLocation Arm64Mir2Lir::LocCReturnFloat() {  in LocCReturnFloat()
103 RegLocation Arm64Mir2Lir::LocCReturnDouble() {  in LocCReturnDouble()
108 RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) {  in TargetReg()
146 ResourceMask Arm64Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const {  in GetRegMaskCommon()
160 ResourceMask Arm64Mir2Lir::GetPCUseDefEncoding() const {  in GetPCUseDefEncoding()
168 void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,  in SetupTargetResourceMasks()
190 ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) {  in ArmConditionEncoding()
284 uint64_t Arm64Mir2Lir::DecodeLogicalImmediate(bool is_wide, int value) {  in DecodeLogicalImmediate()
340 std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) {  in BuildInsnString()
546 void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) {  in DumpResourceMask()
592 bool Arm64Mir2Lir::IsUnconditionalBranch(LIR* lir) {  in IsUnconditionalBranch()
596 RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) {  in RegClassForFieldLoadStore()
606 Arm64Mir2Lir::Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena)  in Arm64Mir2Lir()  function in art::Arm64Mir2Lir
612     DCHECK_EQ(UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode), i)  in Arm64Mir2Lir()
613         << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name  in Arm64Mir2Lir()
615         << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode);  in Arm64Mir2Lir()
621   return new Arm64Mir2Lir(cu, mir_graph, arena);  in Arm64CodeGenerator()
624 void Arm64Mir2Lir::CompilerInitializeRegAlloc() {  in CompilerInitializeRegAlloc()
669 void Arm64Mir2Lir::AdjustSpillMask() {  in AdjustSpillMask()
675 void Arm64Mir2Lir::ClobberCallerSave() {  in ClobberCallerSave()
722 RegLocation Arm64Mir2Lir::GetReturnWideAlt() {  in GetReturnWideAlt()
734 RegLocation Arm64Mir2Lir::GetReturnAlt() {  in GetReturnAlt()
743 void Arm64Mir2Lir::LockCallTemps() {  in LockCallTemps()
764 void Arm64Mir2Lir::FreeCallTemps() {  in FreeCallTemps()
785 RegStorage Arm64Mir2Lir::LoadHelper(QuickEntrypointEnum trampoline) {  in LoadHelper()
792 LIR* Arm64Mir2Lir::CheckSuspendUsingLoad() {  in CheckSuspendUsingLoad()
799 uint64_t Arm64Mir2Lir::GetTargetInstFlags(int opcode) {  in GetTargetInstFlags()
801   return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags;  in GetTargetInstFlags()
804 const char* Arm64Mir2Lir::GetTargetInstName(int opcode) {  in GetTargetInstName()
806   return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name;  in GetTargetInstName()
809 const char* Arm64Mir2Lir::GetTargetInstFmt(int opcode) {  in GetTargetInstFmt()
811   return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt;  in GetTargetInstFmt()
814 RegStorage Arm64Mir2Lir::InToRegStorageArm64Mapper::GetNextReg(ShortyArg arg) {  in GetNextReg()
848 void Arm64Mir2Lir::InstallLiteralPools() {  in InstallLiteralPools()
877 int Arm64Mir2Lir::GenDalvikArgsBulkCopy(CallInfo* /*info*/, int /*first*/, int count) {  in GenDalvikArgsBulkCopy()
885 void Arm64Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) {  in GenMachineSpecificExtendedMethodMIR()