Lines Matching refs:rl_src1

76   void GenMultiplyByConstantFloat(RegLocation rl_dest, RegLocation rl_src1, int32_t constant)
78   void GenMultiplyByConstantDouble(RegLocation rl_dest, RegLocation rl_src1, int64_t constant)
142   void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
144   void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
150   void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
152   void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
154   void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
156   void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
167   void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
171   void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
241   RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_div,
243   RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) OVERRIDE;
270   void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
271   void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
276   void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
278   void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
279   void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,