151 RegLocation MipsMir2Lir::LocCReturn() {  in LocCReturn()
155 RegLocation MipsMir2Lir::LocCReturnRef() {  in LocCReturnRef()
159 RegLocation MipsMir2Lir::LocCReturnWide() {  in LocCReturnWide()
163 RegLocation MipsMir2Lir::LocCReturnFloat() {  in LocCReturnFloat()
167 RegLocation MipsMir2Lir::LocCReturnDouble() {  in LocCReturnDouble()
178 RegStorage MipsMir2Lir::Solo64ToPair64(RegStorage reg) {  in Solo64ToPair64()
187 RegStorage MipsMir2Lir::Fp64ToSolo32(RegStorage reg) {  in Fp64ToSolo32()
196 RegStorage MipsMir2Lir::TargetReg(SpecialTargetRegister reg, WideKind wide_kind) {  in TargetReg()
215 RegStorage MipsMir2Lir::TargetReg(SpecialTargetRegister reg) {  in TargetReg()
250 RegStorage MipsMir2Lir::InToRegStorageMipsMapper::GetNextReg(ShortyArg arg) {  in GetNextReg()
266 RegStorage MipsMir2Lir::InToRegStorageMips64Mapper::GetNextReg(ShortyArg arg) {  in GetNextReg()
294 ResourceMask MipsMir2Lir::GetRegMaskCommon(const RegStorage& reg) const {  in GetRegMaskCommon()
308 ResourceMask MipsMir2Lir::GetPCUseDefEncoding() const {  in GetPCUseDefEncoding()
312 void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, ResourceMask* use_mask,  in SetupTargetResourceMasks()
368 std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {  in BuildInsnString()
465 void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, const ResourceMask& mask, const char *prefix) {  in DumpResourceMask()
516 void MipsMir2Lir::AdjustSpillMask() {  in AdjustSpillMask()
522 void MipsMir2Lir::ClobberCallerSave() {  in ClobberCallerSave()
634 RegLocation MipsMir2Lir::GetReturnWideAlt() {  in GetReturnWideAlt()
640 RegLocation MipsMir2Lir::GetReturnAlt() {  in GetReturnAlt()
647 void MipsMir2Lir::LockCallTemps() {  in LockCallTemps()
661 void MipsMir2Lir::FreeCallTemps() {  in FreeCallTemps()
675 bool MipsMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind ATTRIBUTE_UNUSED) {  in GenMemBarrier()
684 void MipsMir2Lir::CompilerInitializeRegAlloc() {  in CompilerInitializeRegAlloc()
764 RegStorage MipsMir2Lir::LoadHelper(QuickEntrypointEnum trampoline) {  in LoadHelper()
776 LIR* MipsMir2Lir::CheckSuspendUsingLoad() {  in CheckSuspendUsingLoad()
789 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) {  in GenAtomic64Load()
811 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) {  in GenAtomic64Store()
844 void MipsMir2Lir::SpillCoreRegs() {  in SpillCoreRegs()
864 void MipsMir2Lir::UnSpillCoreRegs() {  in UnSpillCoreRegs()
884 bool MipsMir2Lir::IsUnconditionalBranch(LIR* lir) {  in IsUnconditionalBranch()
888 RegisterClass MipsMir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) {  in RegClassForFieldLoadStore()
900 MipsMir2Lir::MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena)  in MipsMir2Lir()  function in art::MipsMir2Lir
908     DCHECK_EQ(MipsMir2Lir::EncodingMap[i].opcode, i)  in MipsMir2Lir()
909         << "Encoding order for " << MipsMir2Lir::EncodingMap[i].name  in MipsMir2Lir()
911         << static_cast<int>(MipsMir2Lir::EncodingMap[i].opcode);  in MipsMir2Lir()
917   return new MipsMir2Lir(cu, mir_graph, arena);  in MipsCodeGenerator()
920 uint64_t MipsMir2Lir::GetTargetInstFlags(int opcode) {  in GetTargetInstFlags()
922   return MipsMir2Lir::EncodingMap[opcode].flags;  in GetTargetInstFlags()
925 const char* MipsMir2Lir::GetTargetInstName(int opcode) {  in GetTargetInstName()
927   return MipsMir2Lir::EncodingMap[opcode].name;  in GetTargetInstName()
930 const char* MipsMir2Lir::GetTargetInstFmt(int opcode) {  in GetTargetInstFmt()
932   return MipsMir2Lir::EncodingMap[opcode].fmt;  in GetTargetInstFmt()