149         info->IsTemp(), info->InUse(), info->IsWide(), info->Partner().GetReg(), info->IsLive(),  in DumpRegPool()
348       if (info->IsWide()) {  in AllocTempBody()
353           DCHECK(partner->IsWide());  in AllocTempBody()
377       if (info->IsWide()) {  in AllocTempBody()
380         DCHECK(partner->IsWide());  in AllocTempBody()
500     if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) {  in AllocLiveReg()
730     DCHECK(info1 && info2 && info1->IsWide() && info2->IsWide() &&  in FlushRegWide()
771   if (info->IsWide()) {  in FlushSpecificReg()
869     if (info_lo->IsWide() && info_lo->Partner().NotExactlyEquals(info_hi->GetReg())) {  in MarkWide()
872     if (info_hi->IsWide() && info_hi->Partner().NotExactlyEquals(info_lo->GetReg())) {  in MarkWide()
934     if (info->IsTemp() && info->IsLive() && info->IsWide() && my_sreg != INVALID_SREG) {  in CheckCorePoolSanity()
939       DCHECK(partner->IsWide());  in CheckCorePoolSanity()
1002       match &= !info->IsWide();  in UpdateLoc()
1029         match &= info_lo->IsWide();  in UpdateLocWide()
1030         match &= info_hi->IsWide();  in UpdateLocWide()
1035         match &= info->IsWide();  in UpdateLocWide()