159     uint32_t disp = target_offset - (adrp_offset & ~0xfffu);  in GenNopsAndAdrpLdr()  local
160     DCHECK_EQ(disp & 3u, 0u);  in GenNopsAndAdrpLdr()
162         ((disp & 0xfffu) << (10 - 2));        // imm12 = ((disp & 0xfffu) >> 2) is at bit 10.  in GenNopsAndAdrpLdr()
164         ((disp & 0x3000u) << (29 - 12)) |     // immlo = ((disp & 0x3000u) >> 12) is at bit 29,  in GenNopsAndAdrpLdr()
165         ((disp & 0xffffc000) >> (14 - 5)) |   // immhi = (disp >> 14) is at bit 5,  in GenNopsAndAdrpLdr()
167         ((disp & 0x80000000) >> (31 - 23));   // sign bit in immhi is at bit 23.  in GenNopsAndAdrpLdr()
549 #define LDRW_PCREL_TEST(adrp_offset, disp) \  argument
550   TEST_F(Arm64RelativePatcherTestDefault, DexCacheReference ## adrp_offset ## WPcRel ## disp) { \
551     TestAdrpLdrPcRelLdr(kLdrWPcRelInsn, disp, adrp_offset, false, 0x12345678u, 0x1234u); \
557 #define LDRX_PCREL_TEST(adrp_offset, disp) \  argument
558   TEST_F(Arm64RelativePatcherTestDefault, DexCacheReference ## adrp_offset ## XPcRel ## disp) { \
559     bool unaligned = ((adrp_offset + 4u + static_cast<uint32_t>(disp)) & 7u) != 0; \
561     TestAdrpLdrPcRelLdr(kLdrXPcRelInsn, disp, adrp_offset, has_thunk, 0x12345678u, 0x1234u); \
567 #define LDRW_SPREL_TEST(adrp_offset, disp) \  argument
568   TEST_F(Arm64RelativePatcherTestDefault, DexCacheReference ## adrp_offset ## WSpRel ## disp) { \
569     TestAdrpLdrSpRelLdr(kLdrWSpRelInsn, disp >> 2, adrp_offset, false, 0x12345678u, 0x1234u); \
574 #define LDRX_SPREL_TEST(adrp_offset, disp) \  argument
575   TEST_F(Arm64RelativePatcherTestDefault, DexCacheReference ## adrp_offset ## XSpRel ## disp) { \
576     TestAdrpLdrSpRelLdr(kLdrXSpRelInsn, disp >> 3, adrp_offset, false, 0x12345678u, 0x1234u); \