Lines Matching refs:SP
705 if ((opcode == ADD || opcode == SUB) && rn == SP && so.IsImmediate()) { in Is32BitDataProcessing()
707 if (rd == SP) { in Is32BitDataProcessing()
1092 if (rd == SP && rn == SP) { in Emit16BitAddSub()
1106 } else if (rd != SP && rn == SP) { in Emit16BitAddSub()
1143 if (rd == SP && rn == SP) { in Emit16BitAddSub()
1374 if (IsHighRegister(rn) && rn != SP && rn != PC) { in EmitLoadStore()
1387 if (rn == SP && offset >= (1 << 10)) { in EmitLoadStore()
1426 if (rn == SP) { in EmitLoadStore()
1531 if (!must_be_32bit && base == SP && bam == (load ? IA_W : DB_W) && in EmitMultiMemOp()
1570 CHECK_EQ((regs & (1 << SP)), 0); in EmitMultiMemOp()
1573 CHECK_EQ((regs & (1 << PC | 1 << SP)), 0); in EmitMultiMemOp()
1808 CHECK_NE(rt, SP); in vmovsr()
1823 CHECK_NE(rt, SP); in vmovrs()
1840 CHECK_NE(rt, SP); in vmovsrr()
1843 CHECK_NE(rt2, SP); in vmovsrr()
1861 CHECK_NE(rt, SP); in vmovrrs()
1864 CHECK_NE(rt2, SP); in vmovrrs()
1882 CHECK_NE(rt, SP); in vmovdrr()
1885 CHECK_NE(rt2, SP); in vmovdrr()
1902 CHECK_NE(rt, SP); in vmovrrd()
1905 CHECK_NE(rt2, SP); in vmovrrd()
2215 str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond); in Push()
2220 ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond); in Pop()
2225 stm(DB_W, SP, regs, cond); in PushList()
2230 ldm(IA_W, SP, regs, cond); in PopList()
2638 if (base == SP) { in StoreToOffset()