992   Mips64ManagedRegister dst = m_dst.AsMips64();  in EmitLoad()
1085     GpuRegister reg = callee_save_regs.at(i).AsMips64().AsGpuRegister();  in BuildFrame()
1091   StoreToOffset(kStoreDoubleword, method_reg.AsMips64().AsGpuRegister(), SP, 0);  in BuildFrame()
1096     Mips64ManagedRegister reg = entry_spills.at(i).AsMips64();  in BuildFrame()
1122     GpuRegister reg = callee_save_regs.at(i).AsMips64().AsGpuRegister();  in RemoveFrame()
1154   Mips64ManagedRegister src = msrc.AsMips64();  in Store()
1179   Mips64ManagedRegister src = msrc.AsMips64();  in StoreRef()
1185   Mips64ManagedRegister src = msrc.AsMips64();  in StoreRawPtr()
1192   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreImmediateToFrame()
1200   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreImmediateToThread64()
1211   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreStackOffsetToThread64()
1223   Mips64ManagedRegister src = msrc.AsMips64();  in StoreSpanning()
1224   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreSpanning()
1239   Mips64ManagedRegister dest = mdest.AsMips64();  in LoadRef()
1246   Mips64ManagedRegister dest = mdest.AsMips64();  in LoadRef()
1247   CHECK(dest.IsGpuRegister() && base.AsMips64().IsGpuRegister());  in LoadRef()
1249                  base.AsMips64().AsGpuRegister(), offs.Int32Value());  in LoadRef()
1261   Mips64ManagedRegister dest = mdest.AsMips64();  in LoadRawPtr()
1262   CHECK(dest.IsGpuRegister() && base.AsMips64().IsGpuRegister());  in LoadRawPtr()
1264                  base.AsMips64().AsGpuRegister(), offs.Int32Value());  in LoadRawPtr()
1269   Mips64ManagedRegister dest = mdest.AsMips64();  in LoadRawPtrFromThread64()
1283   Mips64ManagedRegister dest = mdest.AsMips64();  in Move()
1284   Mips64ManagedRegister src = msrc.AsMips64();  in Move()
1304   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRef()
1313   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRawPtrFromThread64()
1322   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRawPtrToThread64()
1332   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Copy()
1348   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()
1351     LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(),  in Copy()
1355     LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(),  in Copy()
1365   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()
1369     StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(),  in Copy()
1373     StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(),  in Copy()
1388   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()
1391     LoadFromOffset(kLoadWord, scratch, src.AsMips64().AsGpuRegister(), src_offset.Int32Value());  in Copy()
1392 …StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), dest_offset.Int32Value()…  in Copy()
1394     LoadFromOffset(kLoadDoubleword, scratch, src.AsMips64().AsGpuRegister(),  in Copy()
1396     StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(),  in Copy()
1418   Mips64ManagedRegister out_reg = mout_reg.AsMips64();  in CreateHandleScopeEntry()
1419   Mips64ManagedRegister in_reg = min_reg.AsMips64();  in CreateHandleScopeEntry()
1447   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CreateHandleScopeEntry()
1468   Mips64ManagedRegister out_reg = mout_reg.AsMips64();  in LoadReferenceFromHandleScope()
1469   Mips64ManagedRegister in_reg = min_reg.AsMips64();  in LoadReferenceFromHandleScope()
1491   Mips64ManagedRegister base = mbase.AsMips64();  in Call()
1492   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Call()
1502   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Call()
1518   Move(tr.AsMips64().AsGpuRegister(), S1);  in GetCurrentThread()
1527   Mips64ManagedRegister scratch = mscratch.AsMips64();  in ExceptionPoll()