33 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,  in EmitR()  function in art::mips64::Mips64Assembler
95   EmitR(0, rs, rt, rd, 0, 0x20);  in Add()
103   EmitR(0, rs, rt, rd, 0, 0x21);  in Addu()
111   EmitR(0, rs, rt, rd, 0, 0x2d);  in Daddu()
119   EmitR(0, rs, rt, rd, 0, 0x22);  in Sub()
123   EmitR(0, rs, rt, rd, 0, 0x23);  in Subu()
127   EmitR(0, rs, rt, rd, 0, 0x2f);  in Dsubu()
131   EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x18);  in MultR2()
135   EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x19);  in MultuR2()
139   EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1a);  in DivR2()
143   EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1b);  in DivuR2()
147   EmitR(0x1c, rs, rt, rd, 0, 2);  in MulR2()
171   EmitR(0, rs, rt, rd, 2, 0x18);  in MulR6()
175   EmitR(0, rs, rt, rd, 2, 0x1a);  in DivR6()
179   EmitR(0, rs, rt, rd, 3, 0x1a);  in ModR6()
183   EmitR(0, rs, rt, rd, 2, 0x1b);  in DivuR6()
187   EmitR(0, rs, rt, rd, 3, 0x1b);  in ModuR6()
191   EmitR(0, rs, rt, rd, 2, 0x1c);  in Dmul()
195   EmitR(0, rs, rt, rd, 2, 0x1e);  in Ddiv()
199   EmitR(0, rs, rt, rd, 3, 0x1e);  in Dmod()
203   EmitR(0, rs, rt, rd, 2, 0x1f);  in Ddivu()
207   EmitR(0, rs, rt, rd, 3, 0x1f);  in Dmodu()
211   EmitR(0, rs, rt, rd, 0, 0x24);  in And()
219   EmitR(0, rs, rt, rd, 0, 0x25);  in Or()
227   EmitR(0, rs, rt, rd, 0, 0x26);  in Xor()
235   EmitR(0, rs, rt, rd, 0, 0x27);  in Nor()
239   EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x10, 0x20);  in Seb()
243   EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x18, 0x20);  in Seh()
249   EmitR(0x1f, rs, rt, static_cast<GpuRegister>(size_less_one), pos, 3);  in Dext()
253   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);  in Sll()
257   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);  in Srl()
261   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);  in Sra()
265   EmitR(0, rs, rt, rd, 0, 0x04);  in Sllv()
269   EmitR(0, rs, rt, rd, 0, 0x06);  in Srlv()
273   EmitR(0, rs, rt, rd, 0, 0x07);  in Srav()
277   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38);  in Dsll()
281   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a);  in Dsrl()
285   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b);  in Dsra()
289   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3c);  in Dsll32()
293   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e);  in Dsrl32()
297   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f);  in Dsra32()
301   EmitR(0, rs, rt, rd, 0, 0x14);  in Dsllv()
305   EmitR(0, rs, rt, rd, 0, 0x16);  in Dsrlv()
309   EmitR(0, rs, rt, rd, 0, 0x17);  in Dsrav()
353   EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),  in Sync()
358   EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rd, 0, 0x10);  in Mfhi()
362   EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rd, 0, 0x12);  in Mflo()
382   EmitR(0, rs, rt, rd, 0, 0x2a);  in Slt()
386   EmitR(0, rs, rt, rd, 0, 0x2b);  in Sltu()
418   EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09);  in Jalr()
611   EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),  in Break()
616   EmitR(0x0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),  in Nop()