71 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd,  in EmitFR()  argument
74   CHECK_NE(fs, kNoFpuRegister);  in EmitFR()
79                       static_cast<uint32_t>(fs) << kFsShift |  in EmitFR()
514 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {  in AddS()  argument
515   EmitFR(0x11, 0x10, ft, fs, fd, 0x0);  in AddS()
518 void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {  in SubS()  argument
519   EmitFR(0x11, 0x10, ft, fs, fd, 0x1);  in SubS()
522 void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {  in MulS()  argument
523   EmitFR(0x11, 0x10, ft, fs, fd, 0x2);  in MulS()
526 void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {  in DivS()  argument
527   EmitFR(0x11, 0x10, ft, fs, fd, 0x3);  in DivS()
530 void Mips64Assembler::AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {  in AddD()  argument
531   EmitFR(0x11, 0x11, ft, fs, fd, 0x0);  in AddD()
534 void Mips64Assembler::SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {  in SubD()  argument
535   EmitFR(0x11, 0x11, ft, fs, fd, 0x1);  in SubD()
538 void Mips64Assembler::MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {  in MulD()  argument
539   EmitFR(0x11, 0x11, ft, fs, fd, 0x2);  in MulD()
542 void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {  in DivD()  argument
543   EmitFR(0x11, 0x11, ft, fs, fd, 0x3);  in DivD()
546 void Mips64Assembler::MovS(FpuRegister fd, FpuRegister fs) {  in MovS()  argument
547   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6);  in MovS()
550 void Mips64Assembler::MovD(FpuRegister fd, FpuRegister fs) {  in MovD()  argument
551   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x6);  in MovD()
554 void Mips64Assembler::NegS(FpuRegister fd, FpuRegister fs) {  in NegS()  argument
555   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x7);  in NegS()
558 void Mips64Assembler::NegD(FpuRegister fd, FpuRegister fs) {  in NegD()  argument
559   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x7);  in NegD()
562 void Mips64Assembler::Cvtsw(FpuRegister fd, FpuRegister fs) {  in Cvtsw()  argument
563   EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x20);  in Cvtsw()
566 void Mips64Assembler::Cvtdw(FpuRegister fd, FpuRegister fs) {  in Cvtdw()  argument
567   EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x21);  in Cvtdw()
570 void Mips64Assembler::Cvtsd(FpuRegister fd, FpuRegister fs) {  in Cvtsd()  argument
571   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x20);  in Cvtsd()
574 void Mips64Assembler::Cvtds(FpuRegister fd, FpuRegister fs) {  in Cvtds()  argument
575   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x21);  in Cvtds()
578 void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) {  in Mfc1()  argument
579   EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);  in Mfc1()
582 void Mips64Assembler::Mtc1(GpuRegister rt, FpuRegister fs) {  in Mtc1()  argument
583   EmitFR(0x11, 0x04, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);  in Mtc1()
586 void Mips64Assembler::Dmfc1(GpuRegister rt, FpuRegister fs) {  in Dmfc1()  argument
587   EmitFR(0x11, 0x01, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);  in Dmfc1()
590 void Mips64Assembler::Dmtc1(GpuRegister rt, FpuRegister fs) {  in Dmtc1()  argument
591   EmitFR(0x11, 0x05, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);  in Dmtc1()